Patents by Inventor Nan Lin
Nan Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240249871Abstract: A wire-wound inductor using magnetic cores with three air gaps, which comprises a magnetic housing cores, an inner magnetic cores, and coils, characterized in that: multiple size combination of inner magnetic cores can be accepted in the magnetic housing cores with the same size; the magnetic housing cores and the inner magnetic cores can be made of different magnetic materials; the size and the material of the two magnetic parts of the inductor can be selected to meet the requirement of application frequency and power. The inductor adopts the magnetic cores with the air gaps in the mating areas between the magnetic housing core and the inner magnetic core as well as the two inner magnetic cores to form three air gaps. The types of the magnetic cores of the inductors are categorized as PM, RM and PQ by IEC standard. The inductors perform larger saturation current, higher inductance value and lower core loss.Type: ApplicationFiled: April 6, 2023Publication date: July 25, 2024Inventors: Jiu Nan LIN, Tzu To CHU, Chih Ho WU, Chen-Chih LEE
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Patent number: 12044951Abstract: Disclosed is an illumination source comprising a gas delivery system comprising a gas nozzle. The gas nozzle comprises an opening in an exit plane of the gas nozzle. The gas delivery system is configured to provide a gas flow from the opening for generating an emitted radiation at an interaction region. The illumination source is configured to receive a pump radiation having a propagation direction and to provide the pump radiation in the gas flow. A geometry shape of the gas nozzle is adapted to shape a profile of the gas flow such that gas density of the gas flow first increases to a maximum value and subsequently falls sharply in a cut-off region along the propagation direction.Type: GrantFiled: October 7, 2020Date of Patent: July 23, 2024Assignee: ASML Netherlands B.V.Inventors: Wenjie Jin, Nan Lin, Christina Lynn Porter, Petrus Wilhelmus Smorenburg
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Patent number: 12045177Abstract: A data report rate adjustment method for use between a computer host and a peripheral device is provided. According to the actual workload level of the computer host and/or the amount of the input data of the peripheral device, the priority or the report rate of the data to be transmitted from the peripheral device can be dynamically adjusted or set. More especially, the unnecessary data report can be avoided. Consequently, the workload of the computer host can be effectively reduced, and the power consumption of the peripheral device can be saved.Type: GrantFiled: December 7, 2021Date of Patent: July 23, 2024Assignee: PRIMAX ELECTRONICS LTD.Inventors: Shi-Jie Zhang, Che-Yen Huang, Ying-Che Tseng, Chien-Ming Ho, Chien-Nan Lin
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Publication number: 20240243238Abstract: An optoelectronic semiconductor device is provided. The optoelectronic semiconductor device includes a substrate, a semiconductor stack located on the substrate; a first trench and a second trench provided in the semiconductor stack; a first insulating layer filling in the first trench and covering the semiconductor stack; a first metal layer covering the first insulating layer; a second metal layer covering the first insulating layer; and a second insulating layer located between the first metal layer and the first insulating layer, and between the second metal layer and the first insulating layer. A part of the second trench is uncovered by the first insulating layer and the second insulating layer.Type: ApplicationFiled: January 16, 2024Publication date: July 18, 2024Inventors: Ya-Nan Lin, Shih-I Chen, Chun-Ming Wu, Chin-I Lin, Chun-Ru Yang
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Publication number: 20240213190Abstract: A method includes: providing a passivation layer with an embedded MIM capacitor; forming a redistribution layer (RDL) above the passivation layer; and forming an opening in the RDL above the MIM capacitor, wherein the opening separates the RDL into first and second RDL structures, wherein each of the first and second RDL structures has a convex-shaped profile on a sidewall that defines the opening that separates the first RDL structure from the second RDL structure, and wherein the convex-shaped profile on the sidewalls resists stress migration from the RDL to the MIM capacitor to resist stress migration induced cracks forming in the MIM capacitor. The forming an opening includes: removing a portion of the RDL to a first depth using first etching operations; and removing a portion of the RDL to a second depth by laterally etching sidewalls of the first and second RDL structures.Type: ApplicationFiled: February 3, 2023Publication date: June 27, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Nan Lin, Yen-Cheng Lin, Jiann-Horng Lin
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Patent number: 11979283Abstract: An electronic device includes multiple networking devices arranged in a stack. The networking devices may include configurable ports, where a given configurable port in the configurable ports may be configured as a data port or a stacking port. During operation, a networking device in the stack may be designated as a master in the stack. In response, the networking device may provide one or more probe messages to determine a state of the networking devices, where the state includes one or more connections among the networking devices. Then, the networking device may verify that the one or more connections are correct. When the one or more connections are correct, the networking device may define a subset of the configurable ports in the networking devices as stacking ports.Type: GrantFiled: December 17, 2020Date of Patent: May 7, 2024Assignee: Rvckus IP Holdings LLCInventors: Kwun Nan Lin, Ling Yang, Vignesh Hariharan, Robin S Wong
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Publication number: 20240145455Abstract: An electronic package is provided, in which an electronic module including a first electronic element and a second electronic element is disposed on a carrier structure embedded with a third electronic element, and the third electronic element is a photonic chip electrically connected to the electronic module. Therefore, with this configuration, it is beneficial to reduce a layout area of the carrier structure to meet the requirement of miniaturization.Type: ApplicationFiled: January 17, 2023Publication date: May 2, 2024Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Meng-Jie LEE, Chih-Nan LIN, Ci-Hong YAN, Nai-Hao KAO
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Publication number: 20240145379Abstract: Methods and semiconductor devices are provided. A method includes determining a location of a polyimide opening (PIO) corresponding to an under-bump metallization (UBM) feature in a die. The die includes a substrate and an interconnect structure over the substrate. The method also includes determining a location of a stacked via structure in the interconnect structure based on the location of the PIO. The method further includes forming, in the interconnect structure, the stacked via structure comprising at most three stacked contact vias at the location of the PIO.Type: ApplicationFiled: February 23, 2023Publication date: May 2, 2024Inventors: Yen-Kun Lai, Wei-Hsiang Tu, Ching-Ho Cheng, Cheng-Nan Lin, Chiang-Jui Chu, Chien Hao Hsu, Kuo-Chin Chang, Mirng-Ji Lii
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Publication number: 20240145327Abstract: A semiconductor device includes a substrate, an interconnect structure, and conductive vias. The substrate has a first side, a second side and a sidewall connecting the first side and the second side, wherein the sidewall includes a first planar sidewall of a first portion of the substrate, a second planar sidewall of a second portion of the substrate and a curved sidewall of a third portion of the substrate, where the first planar sidewall is connected to the second planar sidewall through the curved sidewall. The interconnect structure is located on the first side of the substrate, where a sidewall of the interconnect structure is offset from the second planar sidewall. The conductive vias are located on the interconnect structure, where the interconnect structure is located between the conductive vias and the substrate.Type: ApplicationFiled: December 27, 2023Publication date: May 2, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chang-Jung Hsueh, Cheng-Nan Lin, Wan-Yu Chiang, Wei-Hung Lin, Ching-Wen Hsiao, Ming-Da Cheng
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Publication number: 20240144430Abstract: A computing system performs artificial-intelligence (AI) super-resolution (SR). The computing system includes multiple processors, which further includes a graphics processing unit (GPU) and an AI processing unit (APU). The computing system also includes a memory to store AI models. When detecting an indication that the loading of the GPU exceeds a threshold, the processors reduce the resolution of a video output from the GPU in response to the indication. One of the AI models is selected based on graphics scenes in the video and the respective power consumption estimates of the AI models. The processors then perform AI SR operations on the video using the selected AI model to restore the resolution of the video for display.Type: ApplicationFiled: October 24, 2023Publication date: May 2, 2024Inventors: Chien-Nan Lin, You-Ming Tsao, Yung-Hsin Chu, An-Li Wang
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Publication number: 20240136291Abstract: Semiconductor devices and methods of forming the same are provided. In some embodiments, a method includes receiving a workpiece having a redistribution layer disposed over and electrically coupled to an interconnect structure. In some embodiments, the method further includes patterning the redistribution layer to form a recess between and separating a first conductive feature and a second conductive feature of the redistribution layer, where corners of the first conductive feature and the second conductive feature are defined adjacent to and on either side of the recess. The method further includes depositing a first dielectric layer over the first conductive feature, the second conductive feature, and within the recess. The method further includes depositing a nitride layer over the first dielectric layer. In some examples, the method further includes removing portions of the nitride layer disposed over the corners of the first conductive feature and the second conductive feature.Type: ApplicationFiled: January 12, 2023Publication date: April 25, 2024Inventors: Hsiang-Ku SHEN, Chen-Chiu HUANG, Chia-Nan LIN, Man-Yun WU, Wen-Tzu CHEN, Sean YANG, Dian-Hao CHEN, Chi-Hao CHANG, Ching-Wei LIN, Wen-Ling CHANG
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Patent number: 11967522Abstract: A method includes depositing an etch stop layer over a first conductive feature, performing a first treatment to amorphize the etch stop layer, depositing a dielectric layer over the etch stop layer, etching the dielectric layer to form an opening, etching-through the etch stop layer to extend the opening into the etch stop layer, and filling the opening with a conductive material to form a second conductive feature.Type: GrantFiled: April 25, 2022Date of Patent: April 23, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jyh-Nan Lin, Chia-Yu Wu, Kai-Shiung Hsu, Ding-I Liu
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Patent number: 11937932Abstract: An acute kidney injury predicting system and a method thereof are proposed. A processor reads the data to be tested, the detection data, the machine learning algorithm and the risk probability comparison table from a main memory. The processor trains the detection data according to the machine learning algorithm to generate an acute kidney injury prediction model, and inputs the data to be tested into the acute kidney injury prediction model to generate an acute kidney injury characteristic risk probability and a data sequence table. The data sequence table lists the data to be tested in sequence according to a proportion of each of the data to be tested in the acute kidney injury characteristics. The processor selects one of the medical treatment data from the risk probability comparison table according to the acute kidney injury characteristic risk probability.Type: GrantFiled: July 8, 2022Date of Patent: March 26, 2024Assignees: TAICHUNG VETERANS GENERAL HOSPITAL, TUNGHAI UNIVERSITYInventors: Chieh-Liang Wu, Chun-Te Huang, Cheng-Hsu Chen, Tsai-Jung Wang, Kai-Chih Pai, Chun-Ming Lai, Min-Shian Wang, Ruey-Kai Sheu, Lun-Chi Chen, Yan-Nan Lin, Chien-Lun Liao, Ta-Chun Hung, Chien-Chung Huang, Chia-Tien Hsu, Shang-Feng Tsai
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Patent number: 11935177Abstract: Disclosed are apparatuses, systems, and techniques to render images with global illumination using efficient ray tracing, light source identification, and reservoir resampling that deploys temporal and spatial reservoirs.Type: GrantFiled: June 15, 2021Date of Patent: March 19, 2024Assignee: Nvidia CorporationInventors: Yaobin Ouyang, Nan Lin, Jacopo Pantaleoni, Markus Kettunen, Shiqiu Liu
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Patent number: 11908136Abstract: A respiratory status classifying method is for classifying as one of at least two respiratory statuses and includes an original physiological parameter inputting step, an original chest image inputting step, a characteristic physiological parameter generating step, a characteristic chest image generating step, a training step and a classifier generating step. The characteristic chest image generating step includes processing at least a part of the original chest images, segmenting images of a left lung, a right lung and a heart from each of the original chest images that are processed, and enhancing image data of the images being segmented, so as to generate a plurality of characteristic chest images. The training step includes training two respiratory status classifiers using a plurality of characteristic physiological parameters and the characteristic chest images by at least one machine learning algorithm.Type: GrantFiled: September 27, 2022Date of Patent: February 20, 2024Assignees: TAICHUNG VETERANS GENERAL HOSPITAL, TUNGHAI UNIVERSITYInventors: Ming-Cheng Chan, Kai-Chih Pai, Wen-Cheng Chao, Yu-Jen Huang, Chieh-Liang Wu, Min-Shian Wang, Chien-Lun Liao, Ta-Chun Hung, Yan-Nan Lin, Hui-Chiao Yang, Ruey-Kai Sheu, Lun-Chi Chen
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Patent number: 11901256Abstract: A semiconductor device includes a substrate, an interconnect structure, and conductive vias. The substrate has a first side, a second side and a sidewall connecting the first side and the second side, wherein the sidewall includes a first planar sidewall of a first portion of the substrate, a second planar sidewall of a second portion of the substrate and a curved sidewall of a third portion of the substrate, where the first planar sidewall is connected to the second planar sidewall through the curved sidewall. The interconnect structure is located on the first side of the substrate, where a sidewall of the interconnect structure is offset from the second planar sidewall. The conductive vias are located on the interconnect structure, where the interconnect structure is located between the conductive vias and the substrate.Type: GrantFiled: August 31, 2021Date of Patent: February 13, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chang-Jung Hsueh, Cheng-Nan Lin, Wan-Yu Chiang, Wei-Hung Lin, Ching-Wen Hsiao, Ming-Da Cheng
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Publication number: 20240040343Abstract: Embodiments of this application provide an information processing method. The method is applied to a system including a first device and a second device, and the first device is connected to the second device. The method includes: The second device receives first information, and sends the first information to the first device, where the first information indicates to perform a target operation. The first device outputs the first information after receiving the first information. The first device receives a first operation. The first device sends a first notification to the second device in response to the first operation. The second device performs the target operation after receiving the first notification.Type: ApplicationFiled: December 13, 2021Publication date: February 1, 2024Inventor: Nan Lin
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Publication number: 20240034641Abstract: A water filter includes a filtering head, a filter bottle assembly, a switch member, and a quick release device. The filtering head includes a flow channel module. The filter bottle assembly includes a filter bottle. The quick release device includes a press lever, two links, and two push members. When the press lever is pivoted, the two links and the two push members are driven by the press lever to move the filter bottle simultaneously so that the filter bottle is mounted on or detached from the filtering head quickly. The a switch member functions as a waterway switch to control a water supply of the filtering head and functions as a locking mechanism for locking or unlocking the quick release device.Type: ApplicationFiled: July 27, 2022Publication date: February 1, 2024Inventors: Sheng-Nan Lin, Hao-Chan Wei, Yi-Wen Liao, Zhe-Hua Ou
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Patent number: 11881746Abstract: An embodiment of the present invention provides a rotor and a motor having the rotor. By providing a plurality of flux barrier groups and slot groups at intervals in a circumferential direction of the rotor iron core, it is possible to flexibly arrange the numbers of the flux barrier groups and the slot groups so as to meet the requirements for the number of poles of different products. In addition, by flexibly adjusting the quantity ratio between the flux barrier groups and the slot groups and/or the quantity relationship between the flux barriers in the flux barrier group and the slots in the slot group, it is possible to meet the requirements for motor efficiency and starting capacity of different products. Further, since the processing jig of the rotor only requires processing of the structures of the flux barriers and the slots, the manufacturing cost can be reduced.Type: GrantFiled: September 3, 2019Date of Patent: January 23, 2024Assignee: NIDEC CORPORATIONInventors: Hsin-Nan Lin, Sheng-Chan Yen, Ta-Yin Luo, Guo-Jhih Yan, Yu-Wei Hsu, Cheng-Tsung Liu
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Publication number: 20240016954Abstract: A composition for improving the solubility of poorly soluble substances is provided. The composition for improving the solubility of poorly soluble substances includes 60-97% by weight of cyclodextrin and/or a derivative thereof, 0.5-4% by weight of at least one water-soluble polymer and 0.4-30% by weight of at least one water-soluble stabilizer, wherein the at least one water-soluble stabilizer includes caffeine, and wherein the poorly soluble substance is a tyrosine kinase inhibitor.Type: ApplicationFiled: September 21, 2023Publication date: January 18, 2024Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Wen-Chia HUANG, Yen-Jen WANG, Felice CHENG, Chia-Ching CHEN, Shao-Chan YIN, Chien Lin PAN, Tsan-Lin HU, Meng-Nan LIN, Kuo-Kuei HUANG, Maggie LU, Chih-Peng LIU