Abstract: A random number generator comprising resistive random-access memory (RRAM) devices including: a first electrode; a second electrode; a third electrode located between the first and second electrode; at least one electrically insulating layer separating the first electrode and the second electrode from the third electrode, wherein the at least one electrically insulating layer has a substantially uniform thickness; a first filament that is current conducting and extends through the at least one electrically insulating layer; a second filament is located in the at least one electrically insulating layer and does not extend through the at least one electrically insulating layer; a voltage source configured to apply voltage to at least one of the first electrode and the second electrode; and a voltage sensor configured to sense voltage of the third electrode in order to determine which one of the first filament or the second filament is more resistive.

Abstract: A device includes a non-volatile analog resistive memory cell. The non-volatile analog resistive memory device includes a resistive memory device and a select transistor. The resistive memory device includes a first terminal and a second terminal. The resistive memory device has a tunable conductance. The select transistor is a ferroelectric field-effect transistor (FeFET) device which includes a gate terminal, a source terminal, and a drain terminal. The gate terminal of the FeFET device is connected to a word line. The source terminal of the FeFET device is connected to a source line. The drain terminal of the FeFET device is connected to the first terminal of the resistive memory device. The second terminal of the resistive memory device is connected to a bit line.

Abstract: A method for system authentication includes subjecting a system to a challenge. The method further includes receiving a response from the system. The received response is dependent upon a location of a filament in a resistive random-access memory device of the system. Additionally, the response is also a unique identifier.

Abstract: A device includes a non-volatile analog resistive memory cell. The non-volatile analog resistive memory device includes a resistive memory device and a select transistor. The resistive memory device includes a first terminal and a second terminal. The resistive memory device has a tunable conductance. The select transistor is a ferroelectric field-effect transistor (FeFET) device which includes a gate terminal, a source terminal, and a drain terminal. The gate terminal of the FeFET device is connected to a word line. The source terminal of the FeFET device is connected to a source line. The drain terminal of the FeFET device is connected to the first terminal of the resistive memory device. The second terminal of the resistive memory device is connected to a bit line.

Abstract: An electronic circuit includes a plurality of word lines; a plurality of bit lines intersecting said plurality of word lines at a plurality of grid points; and a plurality of in-memory processing cells located at said plurality of grid points. Each of said in-memory processing cells includes a first switch having a first terminal coupled to a corresponding one of said word lines and a second terminal; a second switch having a first terminal coupled to said second terminal of said first switch and a second terminal coupled to a corresponding one of said bit lines; and a non-volatile tunable capacitor having one electrode coupled to said second terminal of said first switch and said first terminal of said switch, and having another electrode coupled to ground.

Abstract: An apparatus comprises a phase-change material, a first electrode at a first end of the phase-change material, a second electrode at a second end of the phase-change material, and a heating element coupled to a least a given portion of the phase-change material between the first end and the second end. The apparatus also comprises a first input terminal coupled to the heating element, a second input terminal coupled to the heating element, and an output terminal coupled to the second electrode.

Abstract: Embodiments of the present invention include a phase change memory (PCM) array. The PCM array may include a plurality of PCM cells. Each PCM cell in the plurality of PCM cells may include a top electrode, a resistive element, and a bottom electrode. The PCM array may also include a global heater surrounding the plurality of PCM cells having a thermally conductive material contacting each of the plurality of PCM cells. The global heater may be configured to receive an electric signal to heat the plurality of PCM cells simultaneously.

Abstract: Resistive memory devices are provided which are configured to mitigate resistance drift. A device comprises a phase-change element, a resistive liner, a first electrode, a second electrode, and a third electrode. The resistive liner is disposed in contact with a first surface of the phase-change element. The first electrode is coupled to a first end portion of the resistive liner. The second electrode is coupled to a second end portion of the resistive liner. The third electrode is coupled to the first surface of the phase-change element.

Abstract: A structure including a bottom electrode, a phase change material layer vertically aligned and an ovonic threshold switching layer vertically aligned above the phase change material layer. A structure including a bottom electrode, a phase change material layer and an ovonic threshold switching layer vertically aligned above the phase change material layer, and a first barrier layer physically separating the ovonic threshold switching layer from a top electrode. A method including forming a structure including a liner vertically aligned above a first barrier layer, the first barrier layer vertically aligned above a phase change material layer, the phase change material layer vertically aligned above a bottom electrode, forming a dielectric surrounding the structure, and forming an ovonic threshold switching layer on the first barrier layer, vertical side surfaces of the first buffer layer are vertically aligned with the first buffer layer, the phase change material layer and the bottom electrode.

Abstract: In an approach to a implementing a PUF based on a PCM array, for each PCM device in an array of PCM devices, the PCM device is reset to an initial state. A first conductance of the PCM device is measured. A predetermined number of partial set pulses is applied to the PCM device. A second conductance of the PCM device is measured. Responsive to determining that the second conductance is greater than the first conductance multiplied by a factor, a PUF value of the PCM device is set to logical “1”. Responsive to determining that the second conductance is less than the first conductance multiplied by a factor, a PUF value of the PCM device is set to logical “0”. The PUF value of the PCM device is added to an overall PUF string for the array of PCM devices.

Abstract: An apparatus comprises a phase-change material, a first electrode at a first end of the phase-change material, a second electrode at a second end of the phase-change material, and a heating element coupled to a least a given portion of the phase-change material between the first end and the second end. The apparatus also comprises a first input terminal coupled to the heating element, a second input terminal coupled to the heating element, and an output terminal coupled to the second electrode.

Abstract: In an approach for forming a nonvolatile tunable capacitor device, a first electrode layer is formed distally opposed from a second electrode layer, the first electrode layer configured to make a first electrical connection and the second electrode layer configured to make a second electrical connection. A dielectric layer is posited between the first electrode layer and adjacent to the second electrode layer. A phase change material (PCM) layer is posited between the first electrode layer and the second electrode layer adjacent to the dielectric layer. An energizing component is provided to heat the PCM layer to change a phase of the PCM layer. The energizing component may include a heating element or electrical probe in direct contact with the PCM layer, that when energized is configured to apply heat to the PCM layer. The phase of the PCM layer is changeable between an amorphous phase and a crystalline phase.

Abstract: In a method for using or forming a semiconductor structure. The semiconductor structure may include a resistive random access memory (RRAM) gate with a first electrode and a second electrode. The RRAM gate may also include a switching layer that includes a dielectric material having a switching layer k-value and a switching layer thermal conductivity. The RRAM gate may also include a complimentary switching (CS) mitigation layer with a material having a CS k-value that is lower than the switching layer k-value and a CS thermal conductivity that is higher than the switching layer thermal conductivity.

Abstract: A method is presented for temperature assisted programming of flash memory for neuromorphic computing. The method includes training a chip in an environment having a first temperature, adjusting the first temperature to a second temperature in the environment, and employing the chip for inference in the second temperature environment. The first temperature is about 125° C. or higher and the second temperature is about 50° C. or lower.

Abstract: A physical unclonable function device includes alternating regions of programable material and electrically conductive regions. The regions of programable material are configured to switch resistance upon receiving an electric pulse. An electric pulse applied between two outer electrically conductive regions of the alternating regions will switch the resistance of at least one region of programmable material. The alternating regions may include a plurality of the electrically conducting regions and a region of the programable material disposed between each of the plurality of electrically conductive regions. The resistance of each of the regions of programable material is selectively variable in at least a portion thereof as a result of the electric pulse flowing therethrough. The resistance value of the programable material region may be a readable value as a state of the device. The regions of programmable material may be formed of a phase change material or an oxide.

Abstract: A method of manufacturing a low program voltage flash memory cell with an embedded heater in the control gate creates, on a common device substrate, a conventional flash memory cell in a conventional flash memory area (CFMA), and a neuromorphic computing memory cell in a neuromorphic computing memory area (NCMA). The method comprises providing a flash memory stack in both the CFMA and the NCMA, depositing a heater on top of the flash memory stack in the NCMA without depositing a heater on top of the flash memory stack in the CFMA.

Abstract: A method for forming a nonvolatile PCM logic device may include providing a PCM film component having a first end contact distally opposed from a second end contact, positing a first proximity adjacent to a first surface of the PCM film component, positing a second proximity heater adjacent to a second surface of the PCM film component, wherein the first proximity heater and the second proximity heater are electrically isolated from the PCM film component. The method may further include applying a combination of pulses to one or more of the first proximity heater and the second proximity heater to change a resistance value of the PCM film component corresponding to a logic truth table. Further, the method may include simultaneously applying a first combination of reset pulses to program, or set pulses to initialize, the PCM film component, to the first proximity heater and the second proximity heater.

Abstract: A semiconductor structure comprises a gate structure of a transistor. The gate structure comprises a gate conductive portion disposed on a gate dielectric layer. The semiconductor structure further comprises a capacitor structure disposed on the gate structure. The capacitor structure comprises a first conductive layer, a dielectric layer disposed on the first conductive layer and a second conductive layer disposed on the dielectric layer. The first and second conductive layers are respectively connected to a first contact portion and a second contact portion.

Abstract: Phase change memory devices and methods of forming the same include forming a fin structure from a first material. A phase change memory cell is formed around the fin structure, using a phase change material that includes two solid state phases at an operational temperature.

Abstract: A device for implementing spike-timing-dependent plasticity is provided. The device includes a phase-change element, first and second electrodes disposed respective first and second surfaces of the phase-change element. The phase-change element includes a phase-change material with an inverse resistivity characteristic. The first electrode includes a first heater element, and a first electrical insulating layer which electrically insulates the first resistive heater element from the first electrode and the phase-change element. The second electrode includes a second resistive heater element, and a second electrical insulating layer which electrically insulates the second resistive heater element from the second electrode and the phase-change element.