Patents by Inventor Nancy H. Pratt
Nancy H. Pratt has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10628375Abstract: Methods and systems for enumerating digital circuits in a system-on-a-chip (SOC) are disclosed. The method includes incrementing an enumeration value received from a previous enumerable instance to uniquely identify an immediately adjacent enumerable instance of a plurality of enumerable instances in a daisy chain configuration.Type: GrantFiled: July 9, 2019Date of Patent: April 21, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Thomas B. Chadwick, Jr., Michael R. Ouellette, Nancy H. Pratt
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Patent number: 10628376Abstract: Methods and systems for enumerating digital circuits in a system-on-a-chip (SOC) are disclosed. The method includes incrementing an enumeration value received from a previous enumerable instance to uniquely identify an immediately adjacent enumerable instance of a plurality of enumerable instances in a daisy chain configuration.Type: GrantFiled: July 11, 2019Date of Patent: April 21, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Thomas B. Chadwick, Jr., Michael R. Ouellette, Nancy H. Pratt
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Publication number: 20190332571Abstract: Methods and systems for enumerating digital circuits in a system-on-a-chip (SOC) are disclosed. The method includes incrementing an enumeration value received from a previous enumerable instance to uniquely identify an immediately adjacent enumerable instance of a plurality of enumerable instances in a daisy chain configuration.Type: ApplicationFiled: July 11, 2019Publication date: October 31, 2019Inventors: Thomas B. CHADWICK, JR., Michael R. OUELLETTE, Nancy H. PRATT
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Publication number: 20190332570Abstract: Methods and systems for enumerating digital circuits in a system-on-a-chip (SOC) are disclosed. The method includes incrementing an enumeration value received from a previous enumerable instance to uniquely identify an immediately adjacent enumerable instance of a plurality of enumerable instances in a daisy chain configuration.Type: ApplicationFiled: July 9, 2019Publication date: October 31, 2019Inventors: Thomas B. CHADWICK, JR., Michael R. OUELLETTE, Nancy H. PRATT
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Patent number: 10423570Abstract: Methods and systems for enumerating digital circuits in a system-on-a-chip (SOC) are disclosed. The method includes incrementing an enumeration value received from a previous enumerable instance to uniquely identify an immediately adjacent enumerable instance of a plurality of enumerable instances in a daisy chain configuration.Type: GrantFiled: February 17, 2017Date of Patent: September 24, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Thomas B. Chadwick, Jr., Michael R. Ouellette, Nancy H. Pratt
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Patent number: 10394752Abstract: Methods and systems for enumerating digital circuits in a system-on-a-chip (SOC) are disclosed. The method includes incrementing an enumeration value received from a previous enumerable instance to uniquely identify an immediately adjacent enumerable instance of a plurality of enumerable instances in a daisy chain configuration.Type: GrantFiled: February 17, 2017Date of Patent: August 27, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Thomas B. Chadwick, Jr., Michael R. Ouellette, Nancy H. Pratt
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Publication number: 20170161229Abstract: Methods and systems for enumerating digital circuits in a system-on-a-chip (SOC) are disclosed. The method includes incrementing an enumeration value received from a previous enumerable instance to uniquely identify an immediately adjacent enumerable instance of a plurality of enumerable instances in a daisy chain configuration.Type: ApplicationFiled: February 17, 2017Publication date: June 8, 2017Inventors: Thomas B. CHADWICK, JR., Michael R. OUELLETTE, Nancy H. PRATT
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Publication number: 20170161225Abstract: Methods and systems for enumerating digital circuits in a system-on-a-chip (SOC) are disclosed. The method includes incrementing an enumeration value received from a previous enumerable instance to uniquely identify an immediately adjacent enumerable instance of a plurality of enumerable instances in a daisy chain configuration.Type: ApplicationFiled: February 17, 2017Publication date: June 8, 2017Inventors: Thomas B. CHADWICK, JR., Michael R. OUELLETTE, Nancy H. PRATT
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Patent number: 9672185Abstract: Methods and systems for enumerating digital circuits in a system-on-a-chip (SOC) are disclosed. The method includes incrementing an enumeration value received from a previous enumerable instance to uniquely identify an immediately adjacent enumerable instance of a plurality of enumerable instances in a daisy chain configuration.Type: GrantFiled: September 27, 2013Date of Patent: June 6, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Thomas B. Chadwick, Jr., Michael R. Ouellette, Nancy H. Pratt
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Publication number: 20150095541Abstract: Methods and systems for enumerating digital circuits in a system-on-a-chip (SOC) are disclosed. The method includes incrementing an enumeration value received from a previous enumerable instance to uniquely identify an immediately adjacent enumerable instance of a plurality of enumerable instances in a daisy chain configuration.Type: ApplicationFiled: September 27, 2013Publication date: April 2, 2015Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Thomas B. CHADWICK, Jr., Michael R. OUELLETTE, Nancy H. PRATT
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Patent number: 8935586Abstract: Each register in each built-in self-test (BIST) controller contains a BIST controller-specific start count value that is different from at least one other BIST controller-specific start count. A test controller provides a start command simultaneously to all the BIST controllers. This causes each of the BIST controllers to simultaneously begin a countdown of the BIST controller-specific start count values, using a counter. Each of the BIST controllers starts a test procedure in a corresponding BIST domain when the countdown completes (in the corresponding BIST controller). Thus, the test procedure starts at different times in at least two of the BIST domains based on the difference of the BIST controller-specific start count values in the different registers. Further, during the test procedure, each stagger controller can stagger the start of each BIST engine within the corresponding BIST domain to which the stagger controller is connected.Type: GrantFiled: November 8, 2012Date of Patent: January 13, 2015Assignee: International Business Machines CorporationInventors: Valarie H. Chickanosky, Kevin W. Gorman, Suzanne Granato, Michael R. Ouellette, Nancy H. Pratt, Michael A. Ziegerhofer
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Publication number: 20140129888Abstract: Each register in each built-in self-test (BIST) controller contains a BIST controller-specific start count value that is different from at least one other BIST controller-specific start count. A test controller provides a start command simultaneously to all the BIST controllers. This causes each of the BIST controllers to simultaneously begin a countdown of the BIST controller-specific start count values, using a counter. Each of the BIST controllers starts a test procedure in a corresponding BIST domain when the countdown completes (in the corresponding BIST controller). Thus, the test procedure starts at different times in at least two of the BIST domains based on the difference of the BIST controller-specific start count values in the different registers. Further, during the test procedure, each stagger controller can stagger the start of each BIST engine within the corresponding BIST domain to which the stagger controller is connected.Type: ApplicationFiled: November 8, 2012Publication date: May 8, 2014Applicant: International Business Machines CorporationInventors: Valerie H. Chickanosky, Kevin W. Gorman, Suzanne Granato, Michael R. Ouellette, Nancy H. Pratt, Michael A. Ziegerhofer
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Patent number: 8037337Abstract: A design structure including a digital system. The digital system includes (a) a first logic circuit and a second logic circuit, (b) a first register, (c) a second register, (d) a third register, (e) a clock generator circuit, and (f) a controller circuit. The first logic circuit is capable of obtaining first data and sending second data. The second logic circuit is capable of obtaining the second data and sending third data. The clock generator circuit is capable of asserting (i) a first register clock signal at a first time point, (ii) a second register clock signal at a second time point, and (iii) a third register clock signal at a third time point. The controller circuit is capable of (i) determining a fourth time point, (ii) determining a fifth time point, (iii) controlling the clock generator circuit to assert the second register clock signal.Type: GrantFiled: November 28, 2007Date of Patent: October 11, 2011Assignee: International Business Machines CorporationInventors: Nancy H. Pratt, Sebastian Theodore Ventrone
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Patent number: 7873961Abstract: A method and system for supporting simultaneous operation of operating systems on a single integrated circuit. The system includes a supervisory operating system (SOS) managing execution of instructions, each instruction being executable under one of the operating systems; registers grouped into multiple sets of registers, each set maintaining an identity of one of the operating systems; and a dispatcher capable of dispatching an instruction and a tag attached to the instruction, the tag identifying one of the operating systems and the instruction to be executed under the identified operating system to access one of the registers. One or more of the registers are utilized when the instruction is executed, and are included in a single set of the multiple sets of registers. The single set maintains the identity of the operating system identified by the tag, and each of the one or more registers includes an identifier matching the tag.Type: GrantFiled: July 29, 2005Date of Patent: January 18, 2011Assignee: International Business Machines CorporationInventors: Laura F Miller, Nancy H. Pratt, Sebastian T. Ventrone
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Patent number: 7765351Abstract: A system and method for dynamically managing movement of semaphore data within the system. The system includes, but is no limited to, a plurality of functional units communicating over the network, a memory device communication with the plurality of functional units over the network, and at least one semaphore storage unit communicating with the plurality of functional unites and the memory device over the network. The plurality of functional units include a plurality of functional unit memory locations. The memory device includes a plurality of memory device memory locations. The at least one semaphore storage unit includes a plurality of semaphore storage unit memory locations. The at least one semaphore storage unit controls dynamic movement of the semaphore data among the plurality of functional unit memory locations, the plurality of memory device memory locations, the plurality of semaphore storage unit memory locations, and any combinations therof.Type: GrantFiled: March 12, 2007Date of Patent: July 27, 2010Assignee: International Business Machines CorporationInventors: Pascal A. Nsame, Anthony D. Polson, Nancy H. Pratt, Sebastian T. Ventrone
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Publication number: 20090138676Abstract: A design structure including a digital system. The digital system includes (a) a first logic circuit and a second logic circuit, (b) a first register, (c) a second register, (d) a third register, (e) a clock generator circuit, and (f) a controller circuit. The first logic circuit is capable of obtaining first data and sending second data. The second logic circuit is capable of obtaining the second data and sending third data. The clock generator circuit is capable of asserting (i) a first register clock signal at a first time point, (ii) a second register clock signal at a second time point, and (iii) a third register clock signal at a third time point. The controller circuit is capable of (i) determining a fourth time point, (ii) determining a fifth time point, (iii) controlling the clock generator circuit to assert the second register clock signal.Type: ApplicationFiled: November 28, 2007Publication date: May 28, 2009Inventors: Nancy H. Pratt, Sebastian Theodore Ventrone
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Patent number: 7463083Abstract: A digital system. The digital system includes (a) a first logic circuit and a second logic circuit, (b) a first register, (c) a second register, (d) a third register, (e) a clock generator circuit, and (f) a controller circuit. The first logic circuit is capable of obtaining first data and sending second data. The second logic circuit is capable of obtaining the second data and sending third data. The clock generator circuit is capable of asserting (i) a first register clock signal at a first time point, (ii) a second register clock signal at a second time point, and (iii) a third register clock signal at a third time point. The controller circuit is capable of (i) determining a fourth time point, (ii) determining a fifth time point, (iii) controlling the clock generator circuit to assert the second register clock signal.Type: GrantFiled: November 9, 2007Date of Patent: December 9, 2008Assignee: International Business Machines CorporationInventors: Nancy H. Pratt, Sebastian Theodore Ventrone
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Publication number: 20080229074Abstract: A design structure for an integrated circuit (IC) including a decoder decoding instructions, shadow latches storing instructions as a localized loop, and a state machine controlling the decoder and the plurality of shadow latches. When the state machine identifies instructions that are the same as those stored in the localized loop, it deactivates the decoder and activates the plurality of shadow latches to retrieve and execute the localized loop in place of the instructions provided by the decoder. Additionally, a method of providing localized control caching operations in an IC to reduce power dissipation is provided. The method includes initializing a state machine to control the IC, providing a plurality of shadow latches, decoding a set of instructions, detecting a loop of decoded instructions, caching the loop of decoded instructions in the shadow latches as a localized loop, detecting a loop end signal for the loop and stopping the caching of the localized loop.Type: ApplicationFiled: May 28, 2008Publication date: September 18, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Laura F. Miller, Pascal A. Nsame, Nancy H. Pratt, Sebastian T. Ventrone
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Publication number: 20080229006Abstract: A system and method for dynamically managing movement of semaphore data within the system. The system includes, but is no limited to, a plurality of functional units communicating over the network, a memory device communication with the plurality of functional units over the network, and at least one semaphore storage unit communicating with the plurality of functional unites and the memory device over the network. The plurality of functional units include a plurality of functional unit memory locations. The memory device includes a plurality of memory device memory locations. The at least one semaphore storage unit includes a plurality of semaphore storage unit memory locations. The at least one semaphore storage unit controls dynamic movement of the semaphore data among the plurality of functional unit memory locations, the plurality of memory device memory locations, the plurality of semaphore storage unit memory locations, and any combinations therof.Type: ApplicationFiled: March 12, 2007Publication date: September 18, 2008Inventors: Pascal A. Nsame, Anthony D. Polson, Nancy H. Pratt, Sebastian T. Ventrone
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Patent number: 7317348Abstract: A digital system and a method for operating the same. The digital system includes (a) a first logic circuit and a second logic circuit, (b) a first register, (c) a second register, (d) a third register, (e) a clock generator circuit, and (f) a controller circuit. The first logic circuit is capable of obtaining first data and sending second data. The second logic circuit is capable of obtaining the second data and sending third data. The clock generator circuit is capable of asserting (i) a first register clock signal at a first time point, (ii) a second register clock signal at a second time point, and (iii) a third register clock signal at a third time point. The controller circuit is capable of (i) determining a fourth time point, (ii) determining a fifth time point, (iii) controlling the clock generator circuit to assert the second register clock signal.Type: GrantFiled: January 27, 2006Date of Patent: January 8, 2008Assignee: International Business Machines CorporationInventors: Nancy H. Pratt, Sebastian Theodore Ventrone