Patents by Inventor Nancy M. Lomeli

Nancy M. Lomeli has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210265371
    Abstract: A microelectronic device comprises a stack structure comprising vertically alternating conductive structures and insulating structures arranged in tiers, the tiers individually comprising one of the conductive structures and one of the insulating structures, a staircase structure within the stack structure and having steps comprising edges of at least some of the tiers, conductive contact structures on the steps of the staircase structure, support pillar structures laterally offset in at least a first direction from the conductive contact structures and extending through the stack structure, and bridge structures comprising an electrically insulating material extending vertically through at least a portion of the stack structure and between at least some adjacent support pillar structures of the support pillar structures. Related memory devices, electronic systems, and methods are also described.
    Type: Application
    Filed: February 24, 2020
    Publication date: August 26, 2021
    Inventors: Shuangqiang Luo, Nancy M. Lomeli, Lifang Xu
  • Publication number: 20210265216
    Abstract: A microelectronic device comprises a microelectronic device structure having a memory array region and a staircase region. The microelectronic device structure comprises a stack structure having tiers each comprising a conductive structure and an insulative structure; staircase structures confined within the staircase region and having steps comprising edges of the tiers of the stack structure within the deck and the additional deck; and semiconductive pillar structures confined within the memory array region and extending through the stack structures. The stack structure comprises a deck comprising a group of the tiers; an additional deck overlying the deck and comprising an additional group of the tiers; and an interdeck section between the deck and the additional deck and comprising a dielectric structure confined within the memory array region, and another group of the tiers within vertical boundaries of the dielectric structure and confined within of the staircase region.
    Type: Application
    Filed: February 24, 2020
    Publication date: August 26, 2021
    Inventors: Bo Zhao, Nancy M. Lomeli, Lifang Xu, Adam L. Olson
  • Publication number: 20210257298
    Abstract: Microelectronic devices include stadium structures within a stack structure and substantially symmetrically distributed between a first pillar structure and a second pillar structure, each of which vertically extends through the stack structure. The stack structure includes a vertically alternating sequence of insulative materials and conductive materials arranged in tiers. Each of the stadium structures includes staircase structures having steps including lateral ends of some of the tiers. The substantially symmetrical distribution of the stadium structures, and fill material adjacent such structures, may substantially balance material stresses to avoid or minimize bending of the adjacent pillars. Related methods and systems are also disclosed.
    Type: Application
    Filed: February 13, 2020
    Publication date: August 19, 2021
    Inventors: Lifang Xu, Jian Li, Graham R. Wolstenholme, Paolo Tessariol, George Matamis, Nancy M. Lomeli
  • Patent number: 11056497
    Abstract: A method used in forming a memory array comprises forming a conductive tier atop a substrate, with the conductive tier comprising openings therein. An insulator tier is formed atop the conductive tier and the insulator tier comprises insulator material that extends downwardly into the openings in the conductive tier. A stack comprising vertically-alternating insulative tiers and wordline tiers is formed above the insulator tier. Strings comprising channel material that extend through the insulative tiers and the wordline tiers are formed. The channel material of the strings is directly electrically coupled to conductive material in the conductive tier. Structure independent of method is disclosed.
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: July 6, 2021
    Assignee: Micron Technology, Inc.
    Inventors: John D. Hopkins, Justin B. Dorhout, Damir Fazil, Nancy M. Lomeli
  • Patent number: 11049768
    Abstract: A method of forming a microelectronic device comprises forming a stack structure comprising insulative structures and additional insulative structures vertically alternating with the insulative structures. Apertures are formed to extend to surfaces of the insulative structures at different depths than one another within the stack structure. Dielectric liner structures are formed within the apertures. Sacrificial structures are formed within portions of the apertures remaining unoccupied by the dielectric liner structures. Upper portions of the sacrificial structures are replaced with capping structures. Portions of the insulative structures and remaining portions of the sacrificial structures are replaced with electrically conductive material. Microelectronic devices and electronic systems are also described.
    Type: Grant
    Filed: October 29, 2019
    Date of Patent: June 29, 2021
    Assignee: Micron Technology, Inc.
    Inventors: John D. Hopkins, Jiewei Chen, Nancy M. Lomeli
  • Publication number: 20210167081
    Abstract: Some embodiments include an integrated assembly having a first deck which has first memory cells, and having a second deck which has second memory cells. The first memory cells have first control gate regions which include a first conductive material vertically between horizontally-extending bars of a second conductive material. The second memory cells have second control gate regions which include a fourth conductive material along an outer surface of a third conductive material. A pillar passes through the first and second decks. The pillar includes a dielectric-barrier material laterally surrounding a channel material. The first and fourth materials are directly against the dielectric-barrier material. Some embodiments include methods of forming integrated assemblies.
    Type: Application
    Filed: December 2, 2019
    Publication date: June 3, 2021
    Applicant: Micron Technology, Inc.
    Inventors: John D. Hopkins, Justin B. Dorhout, Nirup Bandaru, Damir Fazil, Nancy M. Lomeli, Jivaan Kishore Jhothiraman, Purnima Narayanan
  • Publication number: 20210143165
    Abstract: Some embodiments include an assembly having channel material structures extending upwardly from a conductive structure. Anchor structures are laterally offset from the channel material structures and penetrate into the conductive structure to a depth sufficient to provide mechanical stability to at least a portion of the assembly. The conductive structure may include a first conductive material over a second conductive material, and may be a source line of a three-dimensional NAND configuration. Some embodiments include methods of forming assemblies to have channel material structures and anchor structures.
    Type: Application
    Filed: December 17, 2020
    Publication date: May 13, 2021
    Applicant: Micron Technology, Inc.
    Inventors: Kunal R. Parekh, Justin B. Dorhout, Nancy M. Lomeli
  • Publication number: 20210125861
    Abstract: A method of forming a microelectronic device comprises forming a stack structure comprising insulative structures and additional insulative structures vertically alternating with the insulative structures. Apertures are formed to extend to surfaces of the insulative structures at different depths than one another within the stack structure. Dielectric liner structures are formed within the apertures. Sacrificial structures are formed within portions of the apertures remaining unoccupied by the dielectric liner structures. Upper portions of the sacrificial structures are replaced with capping structures. Portions of the insulative structures and remaining portions of the sacrificial structures are replaced with electrically conductive material. Microelectronic devices and electronic systems are also described.
    Type: Application
    Filed: October 29, 2019
    Publication date: April 29, 2021
    Inventors: John D. Hopkins, Jiewei Chen, Nancy M. Lomeli
  • Patent number: 10903220
    Abstract: Some embodiments include an assembly having channel material structures extending upwardly from a conductive structure. Anchor structures are laterally offset from the channel material structures and penetrate into the conductive structure to a depth sufficient to provide mechanical stability to at least a portion of the assembly. The conductive structure may include a first conductive material over a second conductive material, and may be a source line of a three-dimensional NAND configuration. Some embodiments include methods of forming assemblies to have channel material structures and anchor structures.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: January 26, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Kunal R. Parekh, Justin B. Dorhout, Nancy M. Lomeli
  • Publication number: 20210013228
    Abstract: Device, systems, and structures include a stack of vertically-alternating tiers of materials arranged in one or more decks of tiers. A channel opening, in which a channel pillar may be formed, extends through the stack. The pillar includes a “shoulder portion” extending laterally into an “undercut portion” of the channel opening, which undercut portion is defined along at least a lower tier of at least one of the decks of the stack.
    Type: Application
    Filed: September 25, 2020
    Publication date: January 14, 2021
    Inventors: John D. Hopkins, Nancy M. Lomeli, Justin B. Dorhout, Damir Fazil
  • Publication number: 20200357809
    Abstract: A method used in forming a memory array comprises forming a conductive tier atop a substrate, with the conductive tier comprising openings therein. An insulator tier is formed atop the conductive tier and the insulator tier comprises insulator material that extends downwardly into the openings in the conductive tier. A stack comprising vertically-alternating insulative tiers and wordline tiers is formed above the insulator tier. Strings comprising channel material that extend through the insulative tiers and the wordline tiers are formed. The channel material of the strings is directly electrically coupled to conductive material in the conductive tier. Structure independent of method is disclosed.
    Type: Application
    Filed: May 9, 2019
    Publication date: November 12, 2020
    Applicant: Micron Technology, Inc.
    Inventors: John D. Hopkins, Justin B. Dorhout, Damir Fazil, Nancy M. Lomeli
  • Patent number: 10825828
    Abstract: Device, systems, and structures include a stack of vertically-alternating tiers of materials arranged in one or more decks of tiers. A channel opening, in which a channel pillar may be formed, extends through the stack. The pillar includes a “shoulder portion” extending laterally into an “undercut portion” of the channel opening, which undercut portion is defined along at least a lower tier of at least one of the decks of the stack.
    Type: Grant
    Filed: October 11, 2018
    Date of Patent: November 3, 2020
    Assignee: Micron Technology, Inc.
    Inventors: John D. Hopkins, Nancy M. Lomeli, Justin B. Dorhout, Damir Fazil
  • Publication number: 20200127004
    Abstract: A method used in forming a memory array comprises forming a stack comprising vertically-alternating insulative tiers and wordline tiers. The stack comprises an insulator tier above the wordline tiers. The insulator tier comprises first insulator material comprising silicon, nitrogen, and one or more of carbon, oxygen, boron, and phosphorus. The first insulator material is patterned to form first horizontally-elongated trenches in the insulator tier. Second insulator material is formed in the first trenches along sidewalls of the first insulator material. The second insulator material is of different composition from that of the first insulator material and narrows the first trenches. After forming the second insulator material, second horizontally-elongated trenches are formed through the insulative tiers and the wordline tiers. The second trenches are horizontally along the narrowed first trenches laterally between and below the second insulator material.
    Type: Application
    Filed: December 21, 2018
    Publication date: April 23, 2020
    Applicant: Micron Technology, Inc.
    Inventors: Justin B. Dorhout, Erik Byers, Merri L. Carlson, Indra V. Chary, Damir Fazil, John D. Hopkins, Nancy M. Lomeli, Eldon Nelson, Joel D. Peterson, Dimitrios Pavlopoulos, Paolo Tessariol, Lifang Xu
  • Publication number: 20200119038
    Abstract: Device, systems, and structures include a stack of vertically-alternating tiers of materials arranged in one or more decks of tiers. A channel opening, in which a channel pillar may be formed, extends through the stack. The pillar includes a “shoulder portion” extending laterally into an “undercut portion” of the channel opening, which undercut portion is defined along at least a lower tier of at least one of the decks of the stack.
    Type: Application
    Filed: October 11, 2018
    Publication date: April 16, 2020
    Inventors: John D. Hopkins, Nancy M. Lomeli, Justin B. Dorhout, Damir Fazil
  • Publication number: 20200075620
    Abstract: Some embodiments include a conductive structure of an integrated circuit. The conductive structure includes an upper primary portion, with the upper primary portion having a first conductive constituent configured as a container. The container has a bottom, and a pair of sidewalls extending upwardly from the bottom. An interior region of the container is over the bottom and between the sidewalls. The upper primary portion includes a second conductive constituent configured as a mass filling the interior region of the container. The second conductive constituent is a different composition than the first conductive constituent. One or more conductive projections join to the upper primary portion and extend downwardly from the upper primary portion. Some embodiments include assemblies comprising memory cells over conductive structures. Some embodiments include methods of forming conductive structures.
    Type: Application
    Filed: August 16, 2019
    Publication date: March 5, 2020
    Applicant: Micron Technology, Inc.
    Inventors: Nancy M. Lomeli, Tom George, Jordan D. Greenlee, Scott M. Pook, John Mark Meldrim
  • Publication number: 20200066747
    Abstract: A method of forming an array of elevationally-extending strings of memory cells comprises forming and removing a portion of lower-stack memory cell material that is laterally across individual bases in individual lower channel openings. Covering material is formed in a lowest portion of the individual lower channel openings to cover the individual bases of the individual lower channel openings. Upper channel openings are formed into an upper stack to the lower channel openings to form interconnected channel openings individually comprising one of the individual lower channel openings and individual of the upper channel openings. A portion of upper-stack memory cell material that is laterally across individual bases in individual upper channel openings is formed and removed. After the removing of the portion of the upper-stack memory cell material, the covering material is removed from the interconnected channel openings.
    Type: Application
    Filed: August 24, 2018
    Publication date: February 27, 2020
    Applicant: Micron Technology, Inc.
    Inventors: Collin Howder, Justin B. Dorhout, Anish A. Khandekar, Mark W. Kiehlbauch, Nancy M. Lomeli
  • Patent number: 10553607
    Abstract: A method of forming an array of elevationally-extending strings of memory cells comprises forming and removing a portion of lower-stack memory cell material that is laterally across individual bases in individual lower channel openings. Covering material is formed in a lowest portion of the individual lower channel openings to cover the individual bases of the individual lower channel openings. Upper channel openings are formed into an upper stack to the lower channel openings to form interconnected channel openings individually comprising one of the individual lower channel openings and individual of the upper channel openings. A portion of upper-stack memory cell material that is laterally across individual bases in individual upper channel openings is formed and removed. After the removing of the portion of the upper-stack memory cell material, the covering material is removed from the interconnected channel openings.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: February 4, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Collin Howder, Justin B. Dorhout, Anish A. Khandekar, Mark W. Kiehlbauch, Nancy M. Lomeli
  • Publication number: 20200013792
    Abstract: Some embodiments include an assembly having channel material structures extending upwardly from a conductive structure. Anchor structures are laterally offset from the channel material structures and penetrate into the conductive structure to a depth sufficient to provide mechanical stability to at least a portion of the assembly. The conductive structure may include a first conductive material over a second conductive material, and may be a source line of a three-dimensional NAND configuration. Some embodiments include methods of forming assemblies to have channel material structures and anchor structures.
    Type: Application
    Filed: September 20, 2019
    Publication date: January 9, 2020
    Applicant: Micron Technology, Inc.
    Inventors: Kunal R. Parekh, Justin B. Dorhout, Nancy M. Lomeli
  • Patent number: 10446566
    Abstract: Some embodiments include an assembly having channel material structures extending upwardly from a conductive structure. Anchor structures are laterally offset from the channel material structures and penetrate into the conductive structure to a depth sufficient to provide mechanical stability to at least a portion of the assembly. The conductive structure may include a first conductive material over a second conductive material, and may be a source line of a three-dimensional NAND configuration. Some embodiments include methods of forming assemblies to have channel material structures and anchor structures.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: October 15, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Kunal R. Parekh, Justin B. Dorhout, Nancy M. Lomeli
  • Patent number: 10446578
    Abstract: A method used in forming an array of elevationally-extending strings of memory cells comprises forming a lower stack comprising vertically-alternating insulative tiers and wordline tiers. Lower channel openings are in the lower stack. A bridge is epitaxially grown that covers individual of the lower channel openings. A lower void space is beneath individual of the bridges in the individual lower channel openings. An upper stack is formed above the lower stack. The upper stack comprises vertically-alternating insulative tiers and wordline tiers. Upper channel openings are formed into the upper stack to the individual bridges to form interconnected channel openings individually comprising one of the individual lower channel openings and individual of the upper channel openings. The interconnected channel openings individually have one of the individual bridges there-across. The individual bridges are penetrated through to uncover individual of the lower void spaces.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: October 15, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Collin Howder, Justin B. Dorhout, Anish A. Khandekar, Mark W. Kiehlbauch, Nancy M. Lomeli