Abstract: Disclosed herein is a coil component that includes a coil part in which a plurality of conductor layers and a plurality of interlayer insulting layers are alternately laminated, and an external terminal. Each of the conductor layers has a coil conductor pattern and an electrode pattern exposed from the coil part. The electrode patterns are connected to each other through a plurality of via conductors penetrating the interlayer insulating layers. At least one of the interlayer insulating layers is exposed from the coil part positioned between the plurality of electrode patterns. The external terminal is formed on the electrode patterns exposed from the coil part so as to avoid an exposed part of the interlayer insulating layer.

Abstract: A first controller controls the DC-DC converter to perform a step-up operation when a voltage on the DC bus is lower than a first reference voltage and controls the DC-DC converter to suspend the step-up operation when the voltage is equal to or higher than the first reference voltage. A second controller controls the inverter to maintain the voltage on the DC bus constant when the voltage on the DC bus is lower than a second reference voltage and controls the inverter to maximize an output power of the inverter when the voltage is equal to or higher than the second reference voltage.

Abstract: Disclosed herein is a coil component that includes: a magnetic element body containing magnetic powder, the magnetic element body having first and second surfaces; a coil conductor embedded in the magnetic element body; and an external terminal connected to the coil conductor and exposed on the first surface of the magnetic element body. The second surface of the magnetic element body is free from the external terminal. The first surface is greater in surface roughness than the second surface.

Abstract: A first controller controls the DC-DC converter to perform a step-up operation when a voltage on the DC bus is lower than a first reference voltage and controls the DC-DC converter to suspend the step-up operation when the voltage is equal to or higher than the first reference voltage. A second controller controls the inverter to maintain the voltage on the DC bus constant when the voltage on the DC bus is lower than a second reference voltage and controls the inverter to maximize an output power of the inverter when the voltage is equal to or higher than the second reference voltage.

Abstract: Provided is a coil component that includes a coil part having a planar coil that includes a winding section and an insulating section covering the winding section, and a magnetic resin layer including a magnetic filler and configured to cover the coil part. The magnetic resin layer has a first magnetic resin layer that is in contact with the coil part and a second magnetic resin layer that is laminated on the first magnetic resin layer. The second magnetic resin layer constitutes a principal surface of the magnetic resin layer, and a maximum particle size of the magnetic filler contained in the second magnetic resin layer is larger than that of the magnetic filler contained in the first magnetic resin layer.

Abstract: A coil component includes a plurality of conductor layers constituted of a first conductor layer to a fourth conductor layer that includes a function layer and a coil layer wound around an axis center; and a covering portion that is formed of an insulative resin, integrally covers the plurality of conductor layers, and is interposed between conductor layers adjacent to each other. The coil layer and the function layer of the plurality of conductor layers have substantially the same shape in a plan view. The fourth conductor layer has a connection conductor layer connecting the coil layer and the function layer to each other. A conductor layer having no connection conductor layer among the plurality of conductor layers has a protrusion portion corresponding to the connection conductor layer at a position overlapping the connection conductor layer in a plan view.

Abstract: Disclosed herein is a coil component that includes a coil part in which a plurality of conductor layers and a plurality of interlayer insulting layers are alternately laminated, and an external terminal. Each of the conductor layers has a coil conductor pattern and an electrode pattern exposed from the coil part. The electrode patterns are connected to each other through a plurality of via conductors penetrating the interlayer insulating layers. At least one of the interlayer insulating layers is exposed from the coil part positioned between the plurality of electrode patterns. The external terminal is formed on the electrode patterns exposed from the coil part so as to avoid an exposed part of the interlayer insulating layer.

Abstract: A printed wiring board includes a core substrate, a first conductive pattern formed on the substrate, an insulation structure having a first insulation layer and formed on the substrate such that the first insulation layer covers the first pattern, a second conductive pattern formed on the structure, and a second insulation layer formed on the structure such that the second insulation layer covers the second pattern. The structure has a via conductor connecting the first and second patterns through the first insulation layer, the first insulation layer includes a first layer containing a reinforcing fiber material and a second layer formed on the first layer such that the first layer is on the substrate side and a second layer is on the second insulation layer side, and the second layer is made of an insulating material which is the same material as an insulating material forming the second insulation layer.

Abstract: A method of manufacturing a multilayered printed wiring board including forming a multilayered core substrate including insulation layers and one or more stacked via structures formed through the insulation layers, the stacked via structure including vias formed in the insulation layers, respectively, the insulation layers in the multilayered core substrate including at least three insulation layers and each of the insulation layers in the multilayered core substrate including a core material impregnated with a resin, and forming a build-up structure over the multilayered core substrate and including interlaminar insulation layers and conductor circuits, each of the interlaminar insulation layers including a resin material without a core material.

Abstract: In one aspect, the invention relates to substituted 4-phenoxyphenol analogs, derivatives thereof, and related compounds, which are useful as inhibitors of proliferating cell nuclear antigen (PCNA); synthetic methods for making the compounds; pharmaceutical compositions comprising the compounds; and methods of treating hyperproliferative disorders associated with PCNA using the compounds and compositions. This abstract is intended as a scanning tool for purposes of searching in the particular art and is not intended to be limiting of the present invention.

Abstract: A method for manufacturing a printed wiring board including providing a structure having a wiring substrate having a conductor circuit, a build-up multilayer structure formed over the wiring substrate and having an outermost conductor circuit and an outermost insulative resin layer, and a solder resist layer formed over the outermost conductor circuit and outermost insulative resin layer and having openings with an opening diameter D for mounting electronic elements, forming conductor pads with a pitch of about 200 pm or less on the outermost conductor circuit in the openings of the solder resist layer, respectively, and forming solder bumps with a height H from a surface of the solder resist layer on the conductor pads on the conductor pads, respectively, such that a ratio H/D is about 0.55 to about 1.0.

Abstract: A printed wiring board including a wiring substrate provided with at least one conductor circuit, a solder resist layer provided on the surface of the wiring substrate, at least one conductor pad formed from a part of the conductor circuit exposed from an opening provided in the solder resist layer, and at least one solder bump for mounting electronic parts on the conductor pad. In the printed wiring board, since the at least one conductor pad is aligned at a pitch of about 200 ?m or less, and a ratio (W/D) of a diameter W of the solder bump to an opening diameter D of the opening formed in the solder resist layer is about 1.05 to about 1.7, connection reliability and insulation reliability can be easily improved.

Abstract: A printed wiring board is manufactured by a method in which a laminate body having a first insulation layer and a conductive film is provided. An alignment mark is formed in the laminate body by removing at least a portion of the conductive film. An electronic component is placed on an adhesive layer provided on the first insulation layer at a position determined based on the alignment mark. After the electronic component is enclosed inside an opening of the second insulation layer, a via hole exposing a terminal of the electronic component is formed at a position determined based on the alignment mark used to determine the position of the electronic component. A via conductor is formed in the via hole, and a conductive layer is formed on the conductive film and patterned to form a conductive circuit connected to the via conductor.

Abstract: A printed wiring board includes a core substrate, a first conductive pattern formed on the substrate, an insulation structure having a first insulation layer and formed on the substrate such that the first insulation layer covers the first pattern, a second conductive pattern formed on the structure, and a second insulation layer formed on the structure such that the second insulation layer covers the second pattern. The structure has a via conductor connecting the first and second patterns through the first insulation layer, the first insulation layer includes a first layer containing a reinforcing fiber material and a second layer formed on the first layer such that the first layer is on the substrate side and a second layer is on the second insulation layer side, and the second layer is made of an insulating material which is the same material as an insulating material forming the second insulation layer.

Abstract: A printed wiring board is manufactured by a method in which a base substrate having a first insulation layer, a second insulation layer, and a conductive film is provided. An electronic component is placed on the first insulation layer at a position determined based on an alignment mark. After the electronic component is enclosed inside an opening of the second insulation layer, a via hole exposing a terminal of the electronic component is formed at a position determined based on the alignment mark, which is used to determine the position of the electronic component. A via conductor is formed in the via hole, and a conductive layer is formed on the conductive film and patterned to form a conductive circuit connected to the via conductor.

Abstract: A multilayered printed wiring board includes a multilayered core substrate having multiple insulation layers and one or more stacked via structure formed through the multiple insulation layers, and a build-up structure formed over the multilayered core substrate and including multiple interlaminar insulation layers and multiple conductor circuits. The stacked via structure has multiple vias formed in the multiple insulation layers, respectively. Each of the interlaminar insulation layers includes a resin material without a core material. The multiple insulation layers in the multilayered core substrate have three or more insulation layers and each of the insulation layers in the multilayered core substrate includes a core material impregnated with a resin.

Abstract: Novel compounds that have been found effective in inhibiting PDZ domain interactions, and particularly interactions of PDZ domains in MAGIs with the oncogenic (tumor suppressor) protein PTEN and interactions between the PDZ domain in the Dishevelled (Dvl) protein and other proteins such as the Frizzled (Fz) protein, have the general formula (I) or (III). The invention also includes combinatorial libraries, arrays and methods for screening and studying proteins using such compounds. Compounds of the invention have produced apoptosis in certain cell lines that overexpress the Dishevelled protein (Dvl), inhibiting Wnt signaling.

Abstract: A method of manufacturing a printed wiring board includes preparing a wiring substrate having a conductive circuit, coating a solder-resist layer over the conductive circuit, leveling a surface of the solder-resist layer so as to obtain a maximum surface roughness in a predetermined range, removing the resin film from the surface of the solder-resist layer, and forming multiple openings in the surface of the solder-resist layer to expose multiple portions of the conductive circuit so as to form multiple conductive pads for mounting an electronic components.

Abstract: A printed wiring board is manufactured by a method in which a base substrate having a first insulation layer, a second insulation layer, and a conductive film is provided. An electronic component is placed on the first insulation layer at a position determined based on an alignment mark. After the electronic component is enclosed inside an opening of the second insulation layer, a via hole exposing a terminal of the electronic component is formed at a position determined based on the alignment mark, which is used to determine the position of the electronic component. A via conductor is formed in the via hole, and a conductive layer is formed on the conductive film and patterned to form a conductive circuit connected to the via conductor.

Abstract: A method of manufacturing a multilayered printed wiring board including forming a multilayered core substrate including insulation layers and one or more stacked via structures formed through the insulation layers, the stacked via structure including vias formed in the insulation layers, respectively, the insulation layers in the multilayered core substrate including at least three insulation layers and each of the insulation layers in the multilayered core substrate including a core material impregnated with a resin, and forming a build-up structure over the multilayered core substrate and including interlaminar insulation layers and conductor circuits, each of the interlaminar insulation layers including a resin material without a core material.