Patents by Inventor Naoaki Fujii

Naoaki Fujii has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8024858
    Abstract: A printed wiring board is manufactured by a method in which a base substrate having a first insulation layer, a second insulation layer, and a conductive film is provided. An electronic component is placed on the first insulation layer at a position determined based on an alignment mark. After the electronic component is enclosed inside an opening of the second insulation layer, a via hole exposing a terminal of the electronic component is formed at a position determined based on the alignment mark, which is used to determine the position of the electronic component. A via conductor is formed in the via hole, and a conductive layer is formed on the conductive film and patterned to form a conductive circuit connected to the via conductor.
    Type: Grant
    Filed: January 12, 2009
    Date of Patent: September 27, 2011
    Assignee: Ibiden Co., Ltd.
    Inventors: Hironori Tanaka, Kazuhiro Yoshikawa, Naoaki Fujii, Atsunari Yamashita
  • Patent number: 8022314
    Abstract: A printed wiring board including a wiring substrate provided with at least one conductor circuit, a solder resist layer provided on the surface of the wiring substrate, at least one conductor pad formed from a part of the conductor circuit exposed from an opening provided in the solder resist layer, and at least one solder bump for mounting electronic parts on the conductor pad. In the printed wiring board, since the at least one conductor pad is aligned at a pitch of about 200 ?m or less, and a ratio (W/D) of a diameter W of the solder bump to an opening diameter D of the opening formed in the solder resist layer is about 1.05 to about 1.7, connection reliability and insulation reliability can be easily improved.
    Type: Grant
    Filed: November 19, 2009
    Date of Patent: September 20, 2011
    Assignee: Ibiden Co., Ltd.
    Inventors: Yoichiro Kawamura, Shigeki Sawa, Katsuhiko Tanno, Hironori Tanaka, Naoaki Fujii
  • Patent number: 8017875
    Abstract: A printed wiring board includes a wiring substrate, one or more conductor circuits provided on the wiring substrate, a solder resist layer provided on a surface of the wiring substrate and having multiple openings, the openings exposing multiple parts of the conductor circuits forming multiple conductor pads for mounting electronic parts, and multiple solder bumps formed on the conductor pads, respectively. The conductor pads are aligned at a pitch of about 200 ?m or less, and a ratio W/D of a diameter W of the solder bumps to an opening diameter D of the openings formed in the solder resist layer is about 1.05 to about 1.7.
    Type: Grant
    Filed: June 29, 2006
    Date of Patent: September 13, 2011
    Assignee: Ibiden Co., Ltd.
    Inventors: Yoichiro Kawamura, Shigeki Sawa, Katsuhiko Tanno, Hironori Tanaka, Naoaki Fujii
  • Publication number: 20110214915
    Abstract: A printed wiring board comprises a wiring substrate provided with at least one conductor circuit, a solder resist layer provided on the surface of the wiring substrate, at least one conductor pad formed from a part of the conductor circuit exposed from an opening provided in the solder resist layer, and at least one solder bump for mounting electronic parts on the conductor pad. In the printed wiring board, since the at least one conductor pad is aligned at a pitch of about 200 ?m or less, and a ratio (W/D) of a diameter W of the solder bump to an opening diameter D of the opening formed in the solder resist layer is about 1.05 to about 1.7, connection reliability and insulation reliability can be easily improved.
    Type: Application
    Filed: May 17, 2011
    Publication date: September 8, 2011
    Applicant: IBIDEN CO., LTD.
    Inventors: Yoichiro KAWAMURA, Shigeki Sawa, Katsuhiko Tanno, Hironori Tanaka, Naoaki Fujii
  • Patent number: 8003897
    Abstract: A printed wiring board includes a wiring substrate provided with at least one conductor circuit, a solder resist layer formed on the surface of the wiring substrate, covering the at least one conductor circuit, conductor pads formed on a part of the at least one conductor circuit exposed from respective openings provided in the solder resist layer for mounting electronic parts, and solder bumps formed on the respective conductor pads. Connection reliability and insulation reliability are easily improved by making the ratio (H/D) of a height H from solder resist layer surface the solder bump to an opening diameter of the opening about 0.55 to about 1.0 even in narrow pitch structure under the pitch of the opening provided in the solder resist layer of about 200 ?m or less.
    Type: Grant
    Filed: February 26, 2010
    Date of Patent: August 23, 2011
    Assignee: Ibiden Co., Ltd.
    Inventors: Yoichiro Kawamura, Shigeki Sawa, Katsuhiko Tanno, Hironori Tanaka, Naoaki Fujii
  • Publication number: 20110160263
    Abstract: Novel compounds that have been found effective in inhibiting PDZ domain interactions, and particularly interactions of PDZ domains in MAGIs with the oncogenic (tumor suppressor) protein PTEN and interactions between the PDZ domain in the Dishevelled (Dvl) protein and other proteins such as the Frizzled (Fz) protein, have the general formula (I) or (III). The invention also includes combinatorial libraries, arrays and methods for screening and studying proteins using such compounds. Compounds of the invention have produced apoptosis in certain cell lines that overexpress the Dishevelled protein (Dvl), inhibiting Wnt signaling.
    Type: Application
    Filed: August 4, 2010
    Publication date: June 30, 2011
    Inventors: Rodney Kiplin Guy, Naoaki Fujii, Liang You, David M. Jablons
  • Patent number: 7935893
    Abstract: A printed wiring board is manufactured by a method in which a laminate body having a first insulation layer and a conductive film is provided. An alignment mark is formed in the laminate body by removing at least a portion of the conductive film. An electronic component is placed on an adhesive layer provided on the first insulation layer at a position determined based on the alignment mark. After the electronic component is enclosed inside an opening of the second insulation layer, a via hole exposing a terminal of the electronic component is formed at a position determined based on the alignment mark used to determine the position of the electronic component. A via conductor is formed in the via hole, and a conductive layer is formed on the conductive film and patterned to form a conductive circuit connected to the via conductor.
    Type: Grant
    Filed: January 12, 2009
    Date of Patent: May 3, 2011
    Assignee: Ibiden Co., Ltd.
    Inventors: Hironori Tanaka, Kazuhiro Yoshikawa, Naoaki Fujii, Atsunari Yamashita
  • Publication number: 20110061232
    Abstract: A method for manufacturing a printed wiring board including providing a structure having a wiring substrate having a conductor circuit, a build-up multilayer structure formed over the wiring substrate and having an outermost conductor circuit and an outermost insulative resin layer, and a solder resist layer formed over the outermost conductor circuit and outermost insulative resin layer and having openings with an opening diameter D for mounting electronic elements, forming conductor pads with a pitch of about 200 pm or less on the outermost conductor circuit in the openings of the solder resist layer, respectively, and forming solder bumps with a height H from a surface of the solder resist layer on the conductor pads on the conductor pads, respectively, such that a ratio H/D is about 0.55 to about 1.0.
    Type: Application
    Filed: November 23, 2010
    Publication date: March 17, 2011
    Applicant: IBIDEN CO., LTD.
    Inventors: Yoichiro Kawamura, Shigeki Sawa, Katsuhiko Tanno, Hironori Tanaka, Naoaki Fujii
  • Patent number: 7795295
    Abstract: Novel compounds that have been found effective in inhibiting PDZ domain interactions, and particularly interactions of PDZ domains in MAGIs with the oncogenic (tumor suppressor) protein PTEN and interactions between the PDZ domain in the Dishevelled (Dvl) protein and other proteins such as the Frizzled (Fz) protein, have the general formula (I) or (III) The invention also includes combinatorial libraries, arrays and methods for screening and studying proteins using such compounds. Compounds of the invention have produced apoptosis in certain cell lines that overexpress the Dishevelled protein (Dvl), inhibiting Wnt signaling.
    Type: Grant
    Filed: June 30, 2005
    Date of Patent: September 14, 2010
    Assignee: The Regents of the University of California
    Inventors: Rodney Kiplin Guy, Naoaki Fujii, Liang You, David M. Jablons
  • Publication number: 20100155129
    Abstract: A printed wiring board comprises a wiring substrate provided with at least one conductor circuit, a solder resist layer formed on the surface of the wiring substrate, covering the at least one conductor circuit, conductor pads formed on a part of the at least one conductor circuit exposed from respective openings provided in the solder resist layer for mounting electronic parts, and solder bumps formed on the respective conductor pads. Connection reliability and insulation reliability are easily improved by making the ratio (H/D) of a height H from solder resist layer surface the solder bump to an opening diameter of the opening about 0.55 to about 1.0 even in narrow pitch structure under the pitch of the opening provided in the solder resist layer of about 200 ?m or less.
    Type: Application
    Filed: February 26, 2010
    Publication date: June 24, 2010
    Applicant: IBIDEN CO., LTD.
    Inventors: Yoichiro KAWAMURA, Shigeki Sawa, Katsuhiko Tanno, Hironori Tanaka, Naoaki Fujii
  • Patent number: 7714233
    Abstract: A printed wiring board including a wiring substrate provided with at least one conductor circuit, a solder resist layer formed on the surface of the wiring substrate, covering the at least one conductor circuit, conductor pads formed on a part of the at least one conductor circuit exposed from respective openings provided in the solder resist layer for mounting electronic parts, and solder bumps formed on the respective conductor pads. The ratio (H/D) of a height H of the solder bumps from solder resist layer surface to an opening diameter of the openings are made to be about 0.55 to about 1.0 with the pitch of the openings provided in the solder resist layer of about 200 ?m or less.
    Type: Grant
    Filed: June 29, 2006
    Date of Patent: May 11, 2010
    Assignee: Ibiden Co., Ltd.
    Inventors: Yoichiro Kawamura, Shigeki Sawa, Katsuhiko Tanno, Hironori Tanaka, Naoaki Fujii
  • Patent number: 7714014
    Abstract: This invention provides compositions, methods and kits for the diagnosis and treatment of cancers expressing a GLI polypeptide, and in particular a GLI1, GLI2 or GLI3 polypeptide. The invention provides small molecule compounds mimicking the transcriptional activation domain of a GLI polypeptide. The small molecule inhibitors of the invention specifically block the activator function of a GLI polypeptide, but not the repressor function of GLI3.
    Type: Grant
    Filed: December 7, 2006
    Date of Patent: May 11, 2010
    Assignee: The Regents of the University of California
    Inventors: Biao He, Naoaki Fujii, Liang You, Zhidong Xu, David M. Jablons
  • Publication number: 20100065323
    Abstract: A printed wiring board comprises a wiring substrate provided with at least one conductor circuit, a solder resist layer provided on the surface of the wiring substrate, at least one conductor pad formed from a part of the conductor circuit exposed from an opening provided in the solder resist layer, and at least one solder bump for mounting electronic parts on the conductor pad. In the printed wiring board, since the at least one conductor pad is aligned at a pitch of about 200 ?m or less, and a ratio (W/D) of a diameter W of the solder bump to an opening diameter D of the opening formed in the solder resist layer is about 1.05 to about 1.7, connection reliability and insulation reliability can be easily improved.
    Type: Application
    Filed: November 19, 2009
    Publication date: March 18, 2010
    Applicant: IBIDEN CO., LTD.
    Inventors: Yoichiro Kawamura, Shigeki Sawa, Katsuhiko Tanno, Hironori Tanaka, Naoaki Fujii
  • Publication number: 20100043942
    Abstract: A printed wiring board is manufactured by a method in which a laminate body having a first insulation layer and a conductive film is provided. An alignment mark is formed in the laminate body by removing at least a portion of the conductive film. An electronic component is placed on an adhesive layer provided on the first insulation layer at a position determined based on the alignment mark. After the electronic component is enclosed inside an opening of the second insulation layer, a via hole exposing a terminal of the electronic component is formed at a position determined based on the alignment mark used to determine the position of the electronic component. A via conductor is formed in the via hole, and a conductive layer is formed on the conductive film and patterned to form a conductive circuit connected to the via conductor.
    Type: Application
    Filed: November 9, 2009
    Publication date: February 25, 2010
    Applicant: IBIDEN CO., LTD.
    Inventors: Hironori Tanaka, Kazuhiro Yoshikawa, Naoaki Fujii, Atsunari Yamashita
  • Patent number: 7601750
    Abstract: Novel compounds that have been found effective in inhibiting PDZ domain interactions, and particularly interactions of PDZ domains in MAGIs with the oncogenic (tumor suppressor) protein PTEN and interactions between the PDZ domain in the Dishevelled (Dvl) protein and other proteins such as the Frizzled (Fz) protein, have the general formula The invention also includes combinatorial libraries, arrays and methods for screening and studying proteins using such compounds. Compounds of the invention have produced apoptosis in certain cell lines that overexpress the Dishevelled protein (Dvl); inhibiting Wnt signaling.
    Type: Grant
    Filed: October 11, 2006
    Date of Patent: October 13, 2009
    Assignee: The Regents of the University of California
    Inventors: R. Kiplin Guy, Irwin D. Kuntz, Jose Haresco, Naoaki Fujii, Kathleen P. Novak, David Stokoe, Biao He, Liang You, Zhidong Xu, David M. Jablons
  • Patent number: 7578625
    Abstract: An optical fiber array 10 includes: a substrate 30 with housing grooves 34 for housing optical fibers 24 formed therein; a cover plate 12 for covering the optical fibers 24 that are housed in the housing grooves 34; and an adhesive layer 16 for joining the substrate 30 with the optical fibers 24 being housed in the housing grooves 34 and the coverplate 12. In the substrate 30, there are formed adhesive grooves 36 for introduction of the adhesive layer 16 between the housing grooves 34 for housing the optical fibers 24 and the end portions of the substrate 30.
    Type: Grant
    Filed: September 29, 2006
    Date of Patent: August 25, 2009
    Assignee: Ibiden Co., Ltd.
    Inventors: Hironori Tanaka, Naoaki Fujii
  • Publication number: 20090205202
    Abstract: A printed wiring board is manufactured by a method in which a base substrate having a first insulation layer, a second insulation layer, and a conductive film is provided. An electronic component is placed on the first insulation layer at a position determined based on an alignment mark. After the electronic component is enclosed inside an opening of the second insulation layer, a via hole exposing a terminal of the electronic component is formed at a position determined based on the alignment mark, which is used to determine the position of the electronic component. A via conductor is formed in the via hole, and a conductive layer is formed on the conductive film and patterned to form a conductive circuit connected to the via conductor.
    Type: Application
    Filed: January 12, 2009
    Publication date: August 20, 2009
    Applicant: IBIDEN CO., LTD.
    Inventors: Hironori Tanaka, Kazuhiro Yoshikawa, Naoaki Fujii, Atsunari Yamashita
  • Publication number: 20090205859
    Abstract: A printed wiring board is manufactured by a method in which a laminate body having a first insulation layer and a conductive film is provided. An alignment mark is formed in the laminate body by removing at least a portion of the conductive film. An electronic component is placed on an adhesive layer provided on the first insulation layer at a position determined based on the alignment mark. After the electronic component is enclosed inside an opening of the second insulation layer, a via hole exposing a terminal of the electronic component is formed at a position determined based on the alignment mark used to determine the position of the electronic component. A via conductor is formed in the via hole, and a conductive layer is formed on the conductive film and patterned to form a conductive circuit connected to the via conductor.
    Type: Application
    Filed: January 12, 2009
    Publication date: August 20, 2009
    Applicant: IBIDEN CO., LTD.
    Inventors: Hironori Tanaka, Kazuhiro Yoshikawa, Naoaki Fujii, Atsunari Yamashita
  • Publication number: 20080149369
    Abstract: A method of manufacturing a printed wiring board includes preparing a wiring substrate having a conductive circuit, coating a solder-resist layer over the conductive circuit, leveling a surface of the solder-resist layer so as to obtain a maximum surface roughness in a predetermined range, removing the resin film from the surface of the solder-resist layer, and forming multiple openings in the surface of the solder-resist layer to expose multiple portions of the conductive circuit so as to form multiple conductive pads for mounting an electronic components.
    Type: Application
    Filed: November 23, 2007
    Publication date: June 26, 2008
    Applicant: IBIDEN CO., LTD.
    Inventors: Yoichiro KAWAMURA, Shigeki SAWA, Katsuhiko TANNO, Hironori TANAKA, Naoaki Fujii
  • Publication number: 20080107863
    Abstract: A multilayered printed wiring board includes a multilayered core substrate having multiple insulation layers and one or more stacked via structure formed through the multiple insulation layers, and a build-up structure formed over the multilayered core substrate and including multiple interlaminar insulation layers and multiple conductor circuits. The stacked via structure has multiple vias formed in the multiple insulation layers, respectively. Each of the interlaminar insulation layers includes a resin material without a core material. The multiple insulation layers in the multilayered core substrate have three or more insulation layers and each of the insulation layers in the multilayered core substrate includes a core material impregnated with a resin.
    Type: Application
    Filed: November 5, 2007
    Publication date: May 8, 2008
    Applicant: IBIDEN CO., LTD
    Inventors: Tomoyuki Ikeda, Naoaki Fujii, Seiji Izawa