Abstract: According to one embodiment, there is provided a memory system including a first generating unit, a buffer unit, a decoding unit, and an update unit. The first generating unit generates logarithm likelihood ratios for plural pieces of data read from a plurality of memory cells. The buffer unit stores the logarithm likelihood ratios. The decoding unit performs first error correction decoding process on the logarithm likelihood ratios, and estimates a logarithm likelihood ratio of data corresponding to an error memory cell among the plural pieces of read data. The update unit updates the logarithm likelihood ratios stored in the buffer unit using the estimated logarithm likelihood ratio.

Abstract: According to one embodiment, a storage device comprises a nonvolatile memory and a memory controller that performs reading and writing data from and into the nonvolatile memory. A number, not being 2n, of threshold areas can be set in the memory cells of the nonvolatile memory. The memory controller performs first writing based on first data value assignment, which sets 2n data values to correspond to 2n threshold areas, in first-time writing into a first memory cell of the nonvolatile memory and performs second writing on the first memory cell after the first writing without erasing data based on second data value assignment, which sets 2n data values to correspond to 2n threshold areas including threshold areas not used in the first data value assignment.

Abstract: According to one embodiment, a memory controller includes a first decoder that decodes a block product code read out from a non-volatile memory and calculates reliability information of each sub-block, and an error cancellation unit that detects a sub-block having many errors based on the reliability information, and performs EXOR operation of a codeword in a column direction including the detected sub-block and a codeword in a row direction including the detected sub-block, and performs decoding using a result of the EXOR operation.

Abstract: According to one embodiment, a storage device comprises a nonvolatile memory and a memory controller that performs reading and writing data from and into the nonvolatile memory. A number, not being 2n, of threshold areas can be set in the memory cells of the nonvolatile memory. The memory controller performs first writing based on first data value assignment, which sets 2n data values to correspond to 2n threshold areas, in first-time writing into a first memory cell of the nonvolatile memory and performs second writing on the first memory cell after the first writing without erasing data based on second data value assignment, which sets 2n data values to correspond to 2n threshold areas including threshold areas not used in the first data value assignment.

Abstract: According to one embodiment, a memory controller in an embodiment includes an encoding unit configured to generate a first parity group from first group data including first and second unit data using G1 (x), generate a second parity group from second group data including third and fourth unit data using G1 (x), and generate a third parity group from the first and second group data and the first and second parity groups using G2 (x), a root of which continues form a root of G1 (x). The memory controller writes the first to fourth unit data and the first to third parity groups in different pages of a nonvolatile memory.

Abstract: According to an embodiment, an error correction decoder includes a first calculation circuit and a second calculation circuit. The first calculation circuit and the second calculation circuit perform the column processing based on the second reliability information corresponding to variable nodes belonging to each of one or more valid blocks arranged in a first row group and the row processing based on the first reliability information corresponding to variable nodes belonging to one or more valid blocks arranged in a second row group whose processing order is later than that of the first row group in parallel.

Abstract: According to one embodiment, an error correction decoder includes a selecting section, calculating section, check section, and updating section. The selecting section selects data used for matrix processing applied to a process target row from LLR data stored in the first memory section based on a check matrix, and stores the data in a second memory section. The calculating section executes the matrix processing based on the data stored in the second memory section, and writes updated data back to the second memory section. The check section checks a parity based on a calculating result of the calculating section. The updating section updates the LLR data of the first memory section based on the updated data of the second memory section.

Abstract: According to one embodiment, a memory controller comprises an encoding unit that encodes first unit data and second unit data to generate a first codeword and a second codeword; a rearranging unit that extracts a first bit string in specific bit positions from each of the first and second codewords to generate first page data and to generate second page data containing the remaining bit strings other than the first bit strings respectively in the first and second codewords; and a write control unit that writes the first page data and the second page data respectively into a first page and a second page of a nonvolatile memory.

Abstract: According to one embodiment, a memory controller includes an encoding unit that executes an error correction coding process on input-data and generates a code word, a calculation control unit that controls whether to execute a multiplication calculation of a multiplication circuit, and a memory interface unit that controls writing of the code word to the memory and reading of the code word from the memory, and the encoding unit includes a remainder circuit that performs a remainder calculation on the input-data using a first generator polynomial and generates a first code word having a first error correction capability and a first multiplication circuit that performs a multiplication calculation on the first code word using a second generator polynomial and performs a multiplication calculation of generating a second code word having a second error correction capability.

Abstract: According to one embodiment, a memory controller includes: a first flash encoding unit that performs flash encoding on user data according to a first scheme to generate user data flash codes; an encoding unit that performs an error correction encoding process on the user data flash codes to generate parities; a second flash encoding unit that performs flash encoding on the parities according to a second scheme to generate parity flash codes; and a memory I/F that writes the user data flash codes and the parity flash codes to the nonvolatile memory.

Abstract: According to one embodiment, a decoder of a memory controller includes: a syndrome calculating unit configured to calculate a syndrome based upon a code word read from the memory; an error locator polynomial generating unit configured to generate an error locator polynomial based upon the syndrome, and to obtain a number of errors based upon the generated error locator polynomial; and an error location calculating unit configured to calculate an error location based upon the error locator polynomial, wherein the process of the error location calculating unit is not executed, when the number of errors is not less than the maximum number of bits that can be corrected by the error locator polynomial generating unit.

Abstract: According to one embodiment, a memory controller is provided, the memory controller including an encoding unit that performs 1st stage error-correction coding on 1st data, performs 2nd stage error-correction coding on 2nd data, and performs 3rd stage error-correction coding on 3rd data, wherein the 1st data includes 4 sub-unit data included in 1st unit data, the 2nd data includes 4 sub-unit data included in the 1st and 2nd unit data, and the 3rd data includes 4 sub-unit data included in the 1st to 4th unit data.

Abstract: According to one embodiment, a memory controller in an embodiment includes an encoding unit configured to generate a first parity group from first group data including first and second unit data using G1 (x), generate a second parity group from second group data including third and fourth unit data using G1 (x), and generate a third parity group from the first and second group data and the first and second parity groups using G2 (x), a root of which continues form a root of G1 (x). The memory controller writes the first to fourth unit data and the first to third parity groups in different pages of a nonvolatile memory.

Abstract: According to one embodiment, a memory controller including a syndrome calculation unit which calculates syndrome based on code word which have the ability to correct t bits, an error locator polynomial calculation unit, and a Chien search unit, wherein the Chien search unit includes a root shift block which shifts all roots, a division block which divides the output from the root shift block by a predetermined polynomial, of which the order is smaller than t, and substitution block which substitutes elements into the remainder polynomial to examine if they are the roots of the remainder, and wherein the predetermined polynomial has at least one root which value is the same as one of the substituted elements.

Abstract: A storage device according to an embodiment includes first and second non-volatile semiconductor memories. In addition, the storage device includes first controller that controls the first non-volatile memory to cause the first non-volatile memory to perform processes. In addition, the storage device includes second controller that controls the second non-volatile memory to cause the second non-volatile memory to perform processes. The storage device further includes a signal line which is connected to the first controller and the second controller and through which a token is transmitted between the first controller and the second controller. The first controller is capable of controlling the first non-volatile memory while holding the token and the second controller is capable of controlling the second non-volatile memory while holding the token.

Abstract: According to one embodiment, a memory controller includes: a first flash encoding unit that performs flash encoding on user data according to a first scheme to generate user data flash codes; an encoding unit that performs an error correction encoding process on the user data flash codes to generate parities; a second flash encoding unit that performs flash encoding on the parities according to a second scheme to generate parity flash codes; and a memory I/F that writes the user data flash codes and the parity flash codes to the nonvolatile memory.

Abstract: A storage device according to an embodiment includes first and second non-volatile semiconductor memories. In addition, the storage device includes first controller that controls the first non-volatile memory to cause the first non-volatile memory to perform processes. In addition, the storage device includes second controller that controls the second non-volatile memory to cause the second non-volatile memory to perform processes. The storage device further includes a signal line which is connected to the first controller and the second controller and through which a token is transmitted between the first controller and the second controller. The first controller is capable of controlling the first non-volatile memory while holding the token and the second controller is capable of controlling the second non-volatile memory while holding the token.

Abstract: According to one embodiment, a memory controller includes an encoding unit that executes an error correction coding process on input-data and generates a code word, a calculation control unit that controls whether to execute a multiplication calculation of a multiplication circuit, and a memory interface unit that controls writing of the code word to the memory and reading of the code word from the memory, and the encoding unit includes a remainder circuit that performs a remainder calculation on the input-data using a first generator polynomial and generates a first code word having a first error correction capability and a first multiplication circuit that performs a multiplication calculation on the first code word using a second generator polynomial and performs a multiplication calculation of generating a second code word having a second error correction capability.

Abstract: According to an embodiment, a semiconductor storage device includes a memory, an encoding unit that generates a parity, and a decoding unit that includes a syndrome calculating unit, an error position polynomial calculating unit, and an error searching and correcting unit, and performs an error correcting process based on data and the parity read from the memory. At the time of performing a compaction process, a process of the error searching and correcting unit is not performed, when the number of error bits acquired by an error position polynomial is equal to or less than a first threshold value based on valid data.

Abstract: According to one embodiment, a memory controller including a syndrome calculation unit which calculates syndrome based on code word which have the ability to correct t bits, an error locator polynomial calculation unit, and a Chien search unit, wherein the Chien search unit includes a root shift block which shifts all roots, a division block which divides the output from the root shift block by a predetermined polynomial, of which the order is smaller than t, and substitution block which substitutes elements into the remainder polynomial to examine if they are the roots of the remainder, and wherein the predetermined polynomial has at least one root which value is the same as one of the substituted elements.