Abstract: A memory system that includes an error check and correct (ECC) circuit is provided. The memory system includes a memory, the ECC circuit, and a processor. The processor controls the entire operation of the memory system. The memory includes a user data region and a management region. The management region stores access information of each of blocks in the user data region as a management table. The value of the access information is either a first value indicating that the number of access times is 0 or a second value indicating that the number of access times is greater than or equal to 1. When the value of the access information of the block is the first value, the circuit checks and corrects an error of data read from the block. When the value of the access information of the block is the second value, the circuit does not check and correct an error of data read from the block.

Abstract: To provide a semiconductor device including element layers that are stacked. A first wiring layer and a second wiring layer are stacked between a first element layer and a second element layer. A third wiring layer and a fourth wiring layer are stacked over the second element layer. Transistors of logic cells are provided in the first element layer. Wirings of the logic cells are provided in the first wiring layer or the second wiring layer. Input ports and output ports of the logic cells are provided in the third wiring layer. The input port of one of the logic cells is connected to the output port of another logic cell through the wiring of the third wiring layer or the fourth wiring layer. Connecting the logic cells through the wiring layers over the second element layer improves the efficiency of steps of arranging and connecting the logic cells.

Abstract: A memory device includes a first memory circuit including a silicon transistor, a selection circuit including a silicon transistor, and a second memory circuit including oxide semiconductor transistors and a storage capacitor, in which one terminal of the storage capacitor is connected to a portion where two oxide semiconductor transistors are connected in series, an output of the second memory circuit is connected to a second input terminal of the selection circuit, and an input of the second memory circuit is connected to a first input terminal of the selection circuit or an output terminal of the first memory circuit.

Abstract: A novel semiconductor device or a semiconductor device whose power consumption can be reduced is provided. The semiconductor device includes a sensor portion, a memory portion, and a control portion. The memory portion has functions of storing multiple detection data and sending them to the control portion. Therefore, a certain amount of detection data acquired through sensing by the sensor portion can be held, and the detection data can be sent to the control portion at a desired timing. Accordingly, in the semiconductor device, the control portion does not need to operate every time information is acquired, and thus, the power supply to the control portion can be completely or partially stopped.

Abstract: A memory device includes a first memory circuit including a silicon transistor, a selection circuit including a silicon transistor, and a second memory circuit including oxide semiconductor transistors and a storage capacitor, in which one terminal of the storage capacitor is connected to a portion where two oxide semiconductor transistors are connected in series, an output of the second memory circuit is connected to a second input terminal of the selection circuit, and an input of the second memory circuit is connected to a first input terminal of the selection circuit or an output terminal of the first memory circuit.

Abstract: A storage system which includes a cache memory needless of replacement of a power storage device, a cache memory with low power consumption, or a cache memory having no limitation on the number of writing operations is provided. An array controller for storing data externally input in any of a plurality of storage devices or a storage system including the array controller includes a processor which specifies at least one of the plurality of storage devices where the data is to be stored and a cache memory which stores the data and outputs the data to the at least one of the plurality of storage devices. The cache memory includes a storage circuit in which a transistor including an oxide semiconductor layer is used.

Abstract: A semiconductor device including a register controller and a processor which includes a register is provided. The register includes a first circuit and a second circuit which includes a plurality of memory portions. The first circuit and the plurality of memory portions can store data by an arithmetic process of the processor. Which of the plurality of memory portions the data is stored in depends on a routine by which the data is processed. The register controller switches the routine in response to an interrupt signal. The register controller can make any one of the plurality of memory portions which corresponds to the routine store the data in the first circuit every time the routine is switched. The register controller can make data stored in any one of the plurality of memory portions which corresponds to the routine be stored in the first circuit every time the routine is switched.

Abstract: To supply a signal in which the occurrence of delays is prevented to a storage circuit. To provide a novel semiconductor device in which a load applied to a logic circuit is low. The following structure is completed: a storage circuit to which a plurality of data signals and a selection signal are supplied connects two combination circuits, and a storage circuit has a function of selecting one of a plurality of data signals in accordance with the selection signal. A selection circuit is not necessarily provided between the storage circuit and the combination circuit. As a result, the combination circuit can supply a signal in which the occurrence of delays is prevented to the storage circuit.

Abstract: This invention provides a semiconductor device with high speed operation and reduced size. A circuit includes a circuit including a memory circuit and a circuit including a logic circuit; thus, the circuit functions as a memory device having a function of storing data and a function of performing logic operation. The circuit can output, in addition to data stored in the circuit, data corresponding to a result of logic operation performed using data stored in the circuit as an input signal. The circuit can directly obtain a result of logic operation from the circuit, and thus, the frequency of input/output of a signal performed between the circuit and the circuit can be reduced.

Abstract: A memory device includes a first memory circuit including a silicon transistor, a selection circuit including a silicon transistor, and a second memory circuit including oxide semiconductor transistors and a storage capacitor, in which one terminal of the storage capacitor is connected to a portion where two oxide semiconductor transistors are connected in series, an output of the second memory circuit is connected to a second input terminal of the selection circuit, and an input of the second memory circuit is connected to a first input terminal of the selection circuit or an output terminal of the first memory circuit.

Abstract: To supply a signal in which the occurrence of delays is prevented to a storage circuit. To provide a novel semiconductor device in which a load applied to a logic circuit is low. The following structure is completed: a storage circuit to which a plurality of data signals and a selection signal are supplied connects two combination circuits, and a storage circuit has a function of selecting one of a plurality of data signals in accordance with the selection signal. A selection circuit is not necessarily provided between the storage circuit and the combination circuit. As a result, the combination circuit can supply a signal in which the occurrence of delays is prevented to the storage circuit.

Abstract: A storage system which includes a cache memory needless of replacement of a power storage device, a cache memory with low power consumption, or a cache memory having no limitation on the number of writing operations is provided. An array controller for storing data externally input in any of a plurality of storage devices or a storage system including the array controller includes a processor which specifies at least one of the plurality of storage devices where the data is to be stored and a cache memory which stores the data and outputs the data to the at least one of the plurality of storage devices. The cache memory includes a storage circuit in which a transistor including an oxide semiconductor layer is used.

Abstract: An object is to give an identification number which is hard to guess from the previous and next identification numbers without overlap, to give an identification number by using a simple program, or to generate rapidly an identification number without using a memory medium having large capacitance. An integer obtained as a set of ciphertexts through bijective mapping from a set of integers which is a plaintext is used as an identification number. In specific, a set of integers without overlap is used as a plaintext space and encryption thereof is performed, so that an element of a ciphertext space obtained from the set of the plaintext space is used as an identification number. As the encryption, a bijective encryption method is employed; for example, RSA cryptosystem or ElGamal cryptosystem can be employed.