Patents by Inventor Naoharu Sugiyama
Naoharu Sugiyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190271083Abstract: According to one embodiment, a film formation apparatus includes a substrate support member, a first gas supplier disposed above the substrate support member and supplying a first gas, a second gas supplier disposed between the substrate support member and the first gas supplier and supplying a second gas, and a plate member disposed between the first gas supplier and the second gas supplier and having a hole, the plate member defining a plasma generation area between the first gas supplier and the plate member, the plasma generation area generating plasma of the first gas, wherein the hole has a diameter between 0.1 to 2 mm and a depth between 0.1 to 5 mm.Type: ApplicationFiled: September 7, 2018Publication date: September 5, 2019Applicant: TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATIONInventors: Yasuhiro ISOBE, Naoharu SUGIYAMA, Takayuki SAKAI, Masaaki ONOMURA
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Publication number: 20190272989Abstract: According to one embodiment, a method of manufacturing a semiconductor device includes generating a plasma of a first gas containing a nitrogen gas and an ammonia gas, supplying a second gas containing nitrogen-containing radicals produced by generating the plasma of the first gas, to a substrate, supplying an organic metal gas containing a group III metallic element to the substrate, and forming a group III nitride semiconductor layer on the substrate by the second gas and the organic metal gas.Type: ApplicationFiled: August 24, 2018Publication date: September 5, 2019Applicant: TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATIONInventors: YASUHIRO ISOBE, NAOHARU SUGIYAMA, Takayuki SAKAI, Kyoichi Suguro
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Publication number: 20180308940Abstract: According to one embodiment, a semiconductor wafer includes a substrate, an AlN buffer layer, a foundation layer, a first high Ga composition layer, a high Al composition layer, a low Al composition layer, an intermediate unit and a second high Ga composition layer. The first layer is provided on the foundation layer. The high Al composition layer is provided on the first layer. The low Al composition layer is provided on the high Al composition layer. The intermediate unit is provided on the low Al composition layer. The second layer is provided on the intermediate unit. The first layer has a first tensile strain and the second layer has a second tensile strain larger than the first tensile strain. Alternatively, the first layer has a first compressive strain and the second layer has a second compressive strain smaller than the first compressive strain.Type: ApplicationFiled: May 18, 2018Publication date: October 25, 2018Applicant: ALPAD CORPORATIONInventors: Yoshiyuki Harada, Toshiki Hikosaka, Hisashi Yoshida, Hung Hung, Naoharu Sugiyama, Shinya Nunoue
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Patent number: 10008571Abstract: According to one embodiment, a semiconductor wafer includes a substrate, an AlN buffer layer, a foundation layer, a first high Ga composition layer, a high Al composition layer, a low Al composition layer, an intermediate unit and a second high Ga composition layer. The first layer is provided on the foundation layer. The high Al composition layer is provided on the first layer. The low Al composition layer is provided on the high Al composition layer. The intermediate unit is provided on the low Al composition layer. The second layer is provided on the intermediate unit. The first layer has a first tensile strain and the second layer has a second tensile strain larger than the first tensile strain. Alternatively, the first layer has a first compressive strain and the second layer has a second compressive strain smaller than the first compressive strain.Type: GrantFiled: October 23, 2015Date of Patent: June 26, 2018Assignee: ALPAD CORPORATIONInventors: Yoshiyuki Harada, Toshiki Hikosaka, Hisashi Yoshida, Hung Hung, Naoharu Sugiyama, Shinya Nunoue
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Publication number: 20170271493Abstract: A semiconductor device includes a first nitride semiconductor layer, a second nitride semiconductor layer containing aluminum located on the first nitride semiconductor layer, a third nitride semiconductor layer with an aluminum concentration higher than that of the second nitride semiconductor layer located on the second nitride semiconductor layer, a drain electrode and a source electrode provided on one of the second nitride semiconductor layer and on the third nitride semiconductor layer, and a gate electrode located between the drain electrode and the source electrode.Type: ApplicationFiled: August 8, 2016Publication date: September 21, 2017Inventors: Akira YOSHIOKA, Takuo KIKUCHI, Junji KATAOKA, Naoharu SUGIYAMA, Hung HUNG, Yasuhiro ISOBE
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Patent number: 9679974Abstract: According to one embodiment, a nitride semiconductor element includes: a stacked body; and a functional layer. The stacked body includes a first GaN layer, a first layer, and a second GaN layer. The first GaN layer includes a first protrusion. The first layer is provided on the first GaN layer and contains at least one of Si and Mg. The second GaN layer is provided on the first layer and includes a second protrusion. Length of bottom of the second protrusion is shorter than length of bottom of the first protrusion. A functional layer is provided on the stacked body and includes a nitride semiconductor.Type: GrantFiled: June 24, 2014Date of Patent: June 13, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Toshiki Hikosaka, Hisashi Yoshida, Hajime Nago, Naoharu Sugiyama, Shinya Nunoue
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Patent number: 9673284Abstract: According to one embodiment, a nitride semiconductor device includes a stacked body and a functional layer. The stacked body includes an AlGaN layer of AlxGa1-xN (0<x?1), a first Si-containing layer, a first GaN layer, a second Si-containing layer, and a second GaN layer. The first Si-containing layer contacts an upper surface of the AlGaN layer. The first Si-containing layer contains Si at a concentration not less than 7×1019/cm3 and not more than 4×1020/cm3. The first GaN layer is provided on the first Si-containing layer. The first GaN layer includes a protrusion having an oblique surface tilted with respect to the upper surface. The second Si-containing layer is provided on the first GaN layer. The second Si-containing layer contains Si. The second GaN layer is provided on the second Si-containing layer. The functional layer is provided on the stacked body. The functional layer includes a nitride semiconductor.Type: GrantFiled: April 16, 2015Date of Patent: June 6, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Toshiki Hikosaka, Yoshiyuki Harada, Hisashi Yoshida, Naoharu Sugiyama, Shinya Nunoue
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Patent number: 9543146Abstract: According to one embodiment, a manufacturing method of a semiconductor device, comprising: forming a first nitride semiconductor layer on a substrate using a first temperature; decreasing a substrate temperature to a second temperature lower than the first temperature, after the forming the first nitride semiconductor layer; forming a second nitride semiconductor layer on the first nitride semiconductor layer using the second temperature; increasing the substrate temperature to a third temperature higher than the first temperature, after the forming the second nitride semiconductor layer; and forming a third nitride semiconductor layer on the second nitride semiconductor layer using the third temperature.Type: GrantFiled: September 1, 2015Date of Patent: January 10, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Naoharu Sugiyama, Yasuhiro Isobe, Hung Hung, Akira Yoshioka
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Publication number: 20160365417Abstract: A semiconductor device includes a first nitride semiconductor layer including carbon and having a first side and an opposing second side. The semiconductor device further includes an intrinsic nitride semiconductor layer on the first nitride semiconductor layer. A first side of the intrinsic semiconductor layer faces the second side of the first nitride semiconductor layer. The semiconductor device further includes a second nitride semiconductor layer including aluminum and disposed on a second side of the intrinsic nitride semiconductor layer opposite to the first nitride semiconductor layer. The first nitride semiconductor layer has a carbon distribution in which a concentration of carbon changes between a high concentration region and a low concentration region. In some embodiments, the high concentration region has a carbon concentration at least 100 times higher than the carbon concentration in the low concentration region.Type: ApplicationFiled: August 26, 2016Publication date: December 15, 2016Inventors: Yasuhiro ISOBE, Naoharu SUGIYAMA
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Patent number: 9508804Abstract: According to one embodiment, a nitride semiconductor element includes a foundation layer, a functional layer and a stacked body. The stacked body is provided between the foundation layer and the functional layer. The stacked body includes a first stacked intermediate layer including a first GaN intermediate layer, a first high Al composition layer of Alx1Ga1-x1N (0<x1?1) and a first low Al composition layer. A compressive strain is applied to the first low Al composition layer. Unstrained GaN has a first lattice spacing. The Alx1Ga1-x1N (0<x1?1) when unstrained has a second lattice spacing. The first high Al composition layer has a third lattice spacing. An Al composition ratio of the first low Al composition layer is not more than a ratio of a difference between the first and third lattice spacings to a difference between the first and second lattice spacings.Type: GrantFiled: February 16, 2016Date of Patent: November 29, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Toshiki Hikosaka, Yoshiyuki Harada, Hisashi Yoshida, Naoharu Sugiyama, Shinya Nunoue
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Patent number: 9478706Abstract: According to one embodiment, a semiconductor light emitting device includes: first and second semiconductor layers, a light emitting part, and an In-containing layer. The first semiconductor layer is formed on a silicon substrate via a foundation layer. The light emitting part is provided on the first semiconductor layer, and includes barrier layers and a well layer provided between the barrier layers including Ga1-z1Inz1N (0<z1?1). The second semiconductor layer is provided on the light emitting part. The In-containing layer is provided at at least one of first and second positions. The first position is between the first semiconductor layer and the light emitting part. The second position is between the second semiconductor layer and the light emitting part. The In-containing layer includes In with a composition ratio different from the In composition ratio z1 and has a thickness 10 nm to 1000 nm.Type: GrantFiled: July 8, 2014Date of Patent: October 25, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Jongil Hwang, Tomonari Shioda, Hung Hung, Naoharu Sugiyama, Shinya Nunoue
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Publication number: 20160268130Abstract: According to one embodiment, a manufacturing method of a semiconductor device, comprising: forming a first nitride semiconductor layer on a substrate using a first temperature; decreasing a substrate temperature to a second temperature lower than the first temperature, after the forming the first nitride semiconductor layer; forming a second nitride semiconductor layer on the first nitride semiconductor layer using the second temperature; increasing the substrate temperature to a third temperature higher than the first temperature, after the forming the second nitride semiconductor layer; and forming a third nitride semiconductor layer on the second nitride semiconductor layer using the third temperature.Type: ApplicationFiled: September 1, 2015Publication date: September 15, 2016Inventors: Naoharu Sugiyama, Yasuhiro Isobe, Hung Hung, Akira Yoshioka
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Patent number: 9419175Abstract: According to one embodiment, a semiconductor light emitting device includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type; a light emitting layer; a conductive metal layer; and a first stress application layer. The first semiconductor layer contains a nitride semiconductor crystal and receives tensile stress in a (0001) plane. The second semiconductor layer contains a nitride semiconductor crystal. The light emitting layer has an average lattice constant larger than a lattice constant of the first semiconductor layer. The conductive metal layer has a thermal expansion coefficient larger than a thermal expansion coefficient of a nitride semiconductor crystal. The first stress application layer is provided between the second semiconductor layer and the light emitting layer. The first stress application layer relaxes tensile stress applied from the metal layer to the second semiconductor layer.Type: GrantFiled: February 28, 2013Date of Patent: August 16, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Naoharu Sugiyama, Shinji Yamada, Shinya Nunoue
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Patent number: 9397167Abstract: A nitride semiconductor wafer includes a silicon substrate, a stacked multilayer unit, a silicon-containing unit, and an upper layer unit. The silicon substrate has a major surface. The stacked multilayer unit is provided on the major surface. The stacked multilayer unit includes N number of buffer layers. The buffer layers include an i-th buffer layer, and an (i+1)-th buffer layer provided on the i-th buffer layer. The i-th buffer layer has an i-th lattice length Wi in a first direction parallel to the major surface. The (i+1)-th buffer layer has an (i+1)-th lattice length W(i+1) in the first direction. A relation that (W(i+1)?Wi)/Wi?0.008 is satisfied for all the buffer layers. The silicon-containing unit is provided on the stacked multilayer unit. The upper layer unit is provided on the silicon-containing unit.Type: GrantFiled: December 28, 2012Date of Patent: July 19, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Hisashi Yoshida, Toshiki Hikosaka, Yoshiyuki Harada, Naoharu Sugiyama, Shinya Nunoue
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Publication number: 20160163803Abstract: According to one embodiment, a nitride semiconductor element includes a foundation layer, a functional layer and a stacked body. The stacked body is provided between the foundation layer and the functional layer. The stacked body includes a first stacked intermediate layer including a first GaN intermediate layer, a first high Al composition layer of Alx1Ga1-x1N (0<x1?1) and a first low Al composition layer. A compressive strain is applied to the first low Al composition layer. Unstrained GaN has a first lattice spacing. The Alx1Ga1-x1N (0<x1?1) when unstrained has a second lattice spacing. The first high Al composition layer has a third lattice spacing. An Al composition ratio of the first low Al composition layer is not more than a ratio of a difference between the first and third lattice spacings to a difference between the first and second lattice spacings.Type: ApplicationFiled: February 16, 2016Publication date: June 9, 2016Applicant: Kabushiki Kaisha ToshibaInventors: Toshiki HIKOSAKA, Yoshiyuki HARADA, Hisashi YOSHIDA, Naoharu SUGIYAMA, Shinya NUNOUE
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Patent number: 9349590Abstract: According to one embodiment, a method for manufacturing a nitride semiconductor layer is disclosed. The method can include forming a first lower layer on a major surface of a substrate and forming a first upper layer on the first lower layer. The first lower layer has a first lattice spacing along a first axis parallel to the major surface. The first upper layer has a second lattice spacing along the first axis larger than the first lattice spacing. At least a part of the first upper layer has compressive strain. A ratio of a difference between the first and second lattice spacing to the first lattice spacing is not less than 0.005 and not more than 0.019. A growth rate of the first upper layer in a direction parallel to the major surface is larger than that in a direction perpendicular to the major surface.Type: GrantFiled: September 5, 2012Date of Patent: May 24, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Toshiki Hikosaka, Yoshiyuki Harada, Hisashi Yoshida, Naoharu Sugiyama, Shinya Nunoue
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Patent number: 9324916Abstract: According to one embodiment, a semiconductor light emitting device includes an electrode layer, a first semiconductor layer, a first elongated electrode, a second semiconductor layer, and a light emitting layer. The first semiconductor layer includes a crystal having a cleavage plane. The first semiconductor layer includes a first thin film portion and a thick film portion. The first thin film portion extends in a first direction perpendicular to a stacking direction from the electrode layer toward the first semiconductor layer. The first thin film portion has a first thickness. The thick film portion is arranged with the first thin film portion in a plane perpendicular to the stacking direction. An angle between the first direction and the cleavage plane is not less than 3 degrees and not more than 27 degrees. The first elongated electrode extends in the first direction in contact with the first thin film portion.Type: GrantFiled: September 29, 2015Date of Patent: April 26, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Jumpei Tajima, Kotaro Zaima, Toshiki Hikosaka, Hiroshi Ono, Naoharu Sugiyama, Shinya Nunoue
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Patent number: 9312436Abstract: According to one embodiment, a nitride semiconductor device includes a first layer and a functional layer. The first layer is formed on an amorphous layer, includes aluminum nitride, and has a compressive strain or a tensile strain. The functional layer is formed on the first layer and includes a nitride semiconductor.Type: GrantFiled: March 15, 2013Date of Patent: April 12, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Ono, Tomonari Shioda, Naoharu Sugiyama, Toshiyuki Oka, Shinya Nunoue
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Patent number: 9305773Abstract: According to one embodiment, a semiconductor device includes a functional layer of a nitride semiconductor. The functional layer is provided on a nitride semiconductor layer including a first stacked multilayer structure provided on a substrate. The first stacked multilayer structure includes a first lower layer, a first intermediate layer, and a first upper layer. The first lower layer contains Si with a first concentration and has a first thickness. The first intermediate layer is provided on the first lower layer to be in contact with the first lower layer, contains Si with a second concentration lower than the first concentration, and has a second thickness thicker than the first thickness. The first upper layer is provided on the first intermediate layer to be in contact with the first intermediate layer, contains Si with a third concentration lower than the second concentration, and has a third thickness.Type: GrantFiled: June 19, 2015Date of Patent: April 5, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Hung Hung, Naoharu Sugiyama, Hisashi Yoshida, Toshiki Hikosaka, Yoshiyuki Harada, Shinya Nunoue
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Publication number: 20160079408Abstract: A semiconductor device includes a silicon substrate, a multi-layered film formed on the silicon substrate, the multi-layered film including a first aluminum nitride containing layer, a second aluminum nitride containing layer, and a film stack having a super lattice structure in which, between the first aluminum nitride containing layer and the second aluminum nitride containing layer, at least two layers selected from a group of layers including an aluminum nitride containing layer, a gallium nitride containing layer and an aluminum gallium nitride containing layer are alternately disposed between the first aluminum nitride containing layer and the second aluminum nitride containing layer, and a first gallium nitride containing layer formed on the multi-layered film.Type: ApplicationFiled: March 3, 2015Publication date: March 17, 2016Inventors: Yasuhiro ISOBE, Naoharu SUGIYAMA