Patents by Inventor Naoharu Sugiyama
Naoharu Sugiyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20150102381Abstract: According to one embodiment, a semiconductor light emitting device includes a first semiconductor layer, a light emitting layer, a second semiconductor layer, and a low refractive index layer. The first semiconductor layer has a first major surface and a second major surface being opposite to the first major surface. The light emitting layer has an active layer provided on the second major surface. The second semiconductor layer is provided on the light emitting layer. The low refractive index layer covers partially the first major surface and has a refractive index lower than the refractive index of the first semiconductor layer.Type: ApplicationFiled: December 19, 2014Publication date: April 16, 2015Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Naoharu SUGIYAMA, Taisuke Sato, Hiroshi Ono, Satoshi Mitsugi, Tomonari Shioda, Jongil Hwang, Hung Hung, Shinya Nunoue
-
Patent number: 9006706Abstract: According to one embodiment, a semiconductor light emitting device includes an n-type semiconductor layer, a p-type semiconductor layer, a light emitting layer, a first intermediate layer, and a second intermediate layer. The n-type and p-type semiconductor layers include a nitride semiconductor. The light emitting layer is provided between the n-type and p-type semiconductor layers, and includes barrier layers and a well layer. A bandgap energy of the well layer is less than that of the barrier layers. The first intermediate layer is provided between the light emitting layer and the p-type semiconductor layer. A bandgap energy of the first intermediate layer is greater than that of the barrier layers. The second intermediate layer includes first and second portions. The first portion is in contact with a p-side barrier layer most proximal to the p-type semiconductor layer. The second portion is in contact with the first intermediate layer.Type: GrantFiled: February 28, 2013Date of Patent: April 14, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Hung Hung, Yoshiyuki Harada, Jongil Hwang, Mitsuhiro Kushibe, Naoharu Sugiyama, Shinya Nunoue
-
Patent number: 8987026Abstract: According to one embodiment, a semiconductor light emitting device includes an n-type layer, a light emitting layer, a p-type layer, and a transparent electrode. The n-type layer includes a nitride semiconductor and has a thickness not more than 500 nm. The light emitting layer is provided on the n-type layer. The p-type layer is provided on the light emitting layer and includes a nitride semiconductor. The transparent electrode contacts the n-type layer. The n-type layer is disposed between the transparent electrode and the light emitting layer.Type: GrantFiled: September 25, 2014Date of Patent: March 24, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Naoharu Sugiyama, Tomonari Shioda, Shigeya Kimura, Koichi Tachibana, Shinya Nunoue
-
Patent number: 8969891Abstract: According to one embodiment, a nitride semiconductor device includes a foundation layer and a functional layer. The foundation layer is formed on an Al-containing nitride semiconductor layer formed on a silicon substrate. The foundation layer has a thickness not less than 1 micrometer and including GaN. The functional layer is provided on the foundation layer. The functional layer includes a first semiconductor layer. The first semiconductor layer has an impurity concentration higher than an impurity concentration in the foundation layer and includes GaN of a first conductivity type.Type: GrantFiled: April 28, 2014Date of Patent: March 3, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Tomonari Shioda, Hung Hung, Jongil Hwang, Taisuke Sato, Naoharu Sugiyama, Shinya Nunoue
-
Publication number: 20150050763Abstract: According to one embodiment, a semiconductor light emitting device includes an n-type layer, a light emitting layer, a p-type layer, and a transparent electrode. The n-type layer includes a nitride semiconductor and has a thickness not more than 500 nm. The light emitting layer is provided on the n-type layer. The p-type layer is provided on the light emitting layer and includes a nitride semiconductor. The transparent electrode contacts the n-type layer. The n-type layer is disposed between the transparent electrode and the light emitting layer.Type: ApplicationFiled: September 25, 2014Publication date: February 19, 2015Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Naoharu SUGIYAMA, Tomonari SHIODA, Shigeya KIMURA, Koichi TACHIBANA, Shinya NUNOUE
-
Patent number: 8952401Abstract: According to one embodiment, a semiconductor light emitting device includes a first semiconductor layer, a light emitting layer, a second semiconductor layer, and a low refractive index layer. The first semiconductor layer has a first major surface and a second major surface being opposite to the first major surface. The light emitting layer has an active layer provided on the second major surface. The second semiconductor layer is provided on the light emitting layer. The low refractive index layer covers partially the first major surface and has a refractive index lower than the refractive index of the first semiconductor layer.Type: GrantFiled: August 29, 2011Date of Patent: February 10, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Naoharu Sugiyama, Taisuke Sato, Hiroshi Ono, Satoshi Mitsugi, Tomonari Shioda, Jongil Hwang, Hung Hung, Shinya Nunoue
-
Publication number: 20150034997Abstract: A semiconductor light emitting element includes a first substrate, a stacked body, an electrode, and a conductive layer. The first substrate has a first face and a first side face. The first side face intersects the first face. The first substrate includes a plurality of conductive portions and a plurality of insulating portions arranged alternately. The stacked body is aligned with the first substrate. The stacked body includes first and second semiconductor layers and a light emitting layer. The electrode is electrically connected to the first semiconductor layer. The conductive layer is electrically connected to at least one of the conductive portions and the second semiconductor layer. At least one of the insulating portions is disposed between the first side face and a portion of the conductive layer nearest to the first side face.Type: ApplicationFiled: July 22, 2014Publication date: February 5, 2015Applicant: Kabushiki Kaisha ToshibaInventors: Jumpei TAJIMA, Shigeya KIMURA, Hiroshi ONO, Naoharu SUGIYAMA, Shinya NUNOUE
-
Publication number: 20150008391Abstract: In general, according to one embodiment, a semiconductor light emitting element includes: a first semiconductor layer; a second semiconductor layer; a light emitting layer. The light emitting layer includes a well layer with a thickness of t1 (nanometers). The well layer includes InxGa1-xN having an In composition ratio x higher than 0 and lower than 1. The first semiconductor layer has a tensile strain of not less than 0.02 percent and not more than 0.25 percent in a plane perpendicular to a stacking direction. A peak wavelength ?p (nanometers) of light satisfies a relationship of ?p=a1+a2×(x+(t1?3.0)×a3). The a1 is not less than 359 and not more than 363. The a2 is not less than 534 and not more than 550. The a3 is not less than 0.0205 and not more than 0.0235.Type: ApplicationFiled: July 3, 2014Publication date: January 8, 2015Applicant: Kabushiki Kaisha ToshibaInventors: Naoharu SUGIYAMA, Shigeya KIMURA, Hisashi YOSHIDA, Toshiki HIKOSAKA, Jumpei TAJIMA, Hajime NAGO, Shinya NUNOUE
-
Patent number: 8928000Abstract: According to one embodiment, a nitride semiconductor wafer includes a silicon substrate, a lower strain relaxation layer provided on the silicon substrate, an intermediate layer provided on the lower strain relaxation layer, an upper strain relaxation layer provided on the intermediate layer, and a functional layer provided on the upper strain relaxation layer. The intermediate layer includes a first lower layer, a first doped layer provided on the first lower layer, and a first upper layer provided on the first doped layer. The first doped layer has a lattice constant larger than or equal to that of the first lower layer and contains an impurity of 1×1018 cm?3 or more and less than 1×1021 cm?3. The first upper layer has a lattice constant larger than or equal to that of the first doped layer and larger than that of the first lower layer.Type: GrantFiled: February 27, 2012Date of Patent: January 6, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Hung Hung, Tomonari Shioda, Jongil Hwang, Naoharu Sugiyama, Shinya Nunoue
-
Publication number: 20150001547Abstract: According to one embodiment, a nitride semiconductor element includes: a stacked body; and a functional layer. The stacked body includes a first GaN layer, a first layer, and a second GaN layer. The first GaN layer includes a first protrusion. The first layer is provided on the first GaN layer and contains at least one of Si and Mg. The second GaN layer is provided on the first layer and includes a second protrusion. Length of bottom of the second protrusion is shorter than length of bottom of the first protrusion. A functional layer is provided on the stacked body and includes a nitride semiconductor.Type: ApplicationFiled: June 24, 2014Publication date: January 1, 2015Applicant: Kabushiki Kaisha ToshibaInventors: Toshiki HIKOSAKA, Hisashi Yoshida, Hajime Nago, Naoharu Sugiyama, Shinya Nunoue
-
Patent number: 8884307Abstract: According to one embodiment, a nitride semiconductor wafer includes a silicon substrate, a lower strain relaxation layer provided on the silicon substrate, an intermediate layer provided on the lower strain relaxation layer, an upper strain relaxation layer provided on the intermediate layer, and a functional layer provided on the upper strain relaxation layer. The intermediate layer includes a first lower layer, a first doped layer provided on the first lower layer, and a first upper layer provided on the first doped layer. The first doped layer has a lattice constant larger than or equal to that of the first lower layer and contains an impurity of 1×1018 cm?3 or more and less than 1×1021 cm?3. The first upper layer has a lattice constant larger than or equal to that of the first doped layer and larger than that of the first lower layer.Type: GrantFiled: February 27, 2012Date of Patent: November 11, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Hung Hung, Tomonari Shioda, Jongil Hwang, Naoharu Sugiyama, Shinya Nunoue
-
Patent number: 8878213Abstract: According to one embodiment, a semiconductor light emitting device includes an n-type layer, a light emitting layer, a p-type layer, and a transparent electrode. The n-type layer includes a nitride semiconductor and has a thickness not more than 500 nm. The light emitting layer is provided on the n-type layer. The p-type layer is provided on the light emitting layer and includes a nitride semiconductor. The transparent electrode contacts the n-type layer. The n-type layer is disposed between the transparent electrode and the light emitting layer.Type: GrantFiled: August 29, 2011Date of Patent: November 4, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Naoharu Sugiyama, Tomonari Shioda, Shigeya Kimura, Koichi Tachibana, Shinya Nunoue
-
Publication number: 20140319457Abstract: According to one embodiment, a semiconductor light emitting device includes: first and second semiconductor layers, a light emitting part, and an In-containing layer. The first semiconductor layer is formed on a silicon substrate via a foundation layer. The light emitting part is provided on the first semiconductor layer, and includes barrier layers and a well layer provided between the barrier layers including Ga1-z1Inz1N (0<z1?1). The second semiconductor layer is provided on the light emitting part. The In-containing layer is provided at at least one of first and second positions. The first position is between the first semiconductor layer and the light emitting part. The second position is between the second semiconductor layer and the light emitting part. The In-containing layer includes In with a composition ratio different from the In composition ratio z1 and has a thickness 10 nm to 1000 nm.Type: ApplicationFiled: July 8, 2014Publication date: October 30, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Jongil HWANG, Tomonari SHIODA, Hung HUNG, Naoharu SUGIYAMA, Shinya NUNOUE
-
Patent number: 8872158Abstract: According to one embodiment, a semiconductor light emitting device includes an n-type semiconductor layer, a p-type semiconductor layer, and a light emitting part. The n-type semiconductor layer includes a nitride semiconductor. The p-type semiconductor layer includes a nitride semiconductor. The light emitting part is provided between the n-type and the p-type semiconductor layers and includes an n-side barrier layer and a first light emitting layer. The first light emitting layer includes a first barrier layer, a first well layer, and a first AIGaN layer. The first barrier layer is provided between the n-side barrier layer and the p-type semiconductor layer. The first well layer contacts the n-side barrier layer between the n-side and the first barrier layer. The first AIGaN layer is provided between the first well layer and the first barrier layer. A peak wavelength ?p of light emitted from the light emitting part is longer than 515 nanometers.Type: GrantFiled: February 20, 2014Date of Patent: October 28, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Tomonari Shioda, Hisashi Yoshida, Naoharu Sugiyama, Shinya Nunoue
-
Publication number: 20140264413Abstract: A semiconductor light emitting element includes a stacked body, a first metal layer, and a second metal layer. The stacked body includes a first semiconductor layer, a second semiconductor layer, and a light emitting layer. The second semiconductor layer is separated from the first semiconductor layer in a first direction. The light emitting layer is provided between the first semiconductor layer and the second semiconductor layer. The first metal layer is stacked with the stacked body in the first direction to be electrically connected to one selected from the first semiconductor layer and the second semiconductor layer. The first metal layer has a side surface extending in the first direction. The second metal layer covers at least a portion of the side surface of the first metal layer. A reflectance of the second metal layer is higher than a reflectance of the first metal layer.Type: ApplicationFiled: February 7, 2014Publication date: September 18, 2014Applicant: Kabushiki Kaisha ToshibaInventors: Shinji YAMADA, Hiroshi KATSUNO, Satoshi MITSUGI, Naoharu SUGIYAMA, Shinya NUNOUE
-
Patent number: 8835983Abstract: According to one embodiment, a nitride semiconductor wafer includes a silicon substrate, a lower strain relaxation layer provided on the silicon substrate, an intermediate layer provided on the lower strain relaxation layer, an upper strain relaxation layer provided on the intermediate layer, and a functional layer provided on the upper strain relaxation layer. The intermediate layer includes a first lower layer, a first doped layer provided on the first lower layer, and a first upper layer provided on the first doped layer. The first doped layer has a lattice constant larger than or equal to that of the first lower layer and contains an impurity of 1×1018 cm?3 or more and less than 1×1021 cm?3. The first upper layer has a lattice constant larger than or equal to that of the first doped layer and larger than that of the first lower layer.Type: GrantFiled: October 24, 2013Date of Patent: September 16, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Hung Hung, Tomonari Shioda, Jongil Hwang, Naoharu Sugiyama, Shinya Nunoue
-
Publication number: 20140252310Abstract: A semiconductor light emitting device includes a stacked body and an optical member. The stacked body includes a first semiconductor layer, a second semiconductor, and a light emitting layer. The second semiconductor layer is separated from the first semiconductor layer in a first direction. The light emitting layer is provided between the first semiconductor layer and the second semiconductor layer. The optical member is stacked with the stacked body in the first direction. The optical member is light-transmissive. The length of the optical member in the first direction is longer than a length of the first semiconductor layer in the first direction. The surface area of the optical member projected onto a plane perpendicular to the first direction is less than a surface area of the stacked body projected onto the plane.Type: ApplicationFiled: January 31, 2014Publication date: September 11, 2014Applicant: Kabushiki Kaisha ToshibaInventors: Hiroshi ONO, Satoshi Mitsugi, Hiroshi Katsuno, Naoharu Sugiyama, Shinya Nunoue
-
Patent number: 8816367Abstract: According to one embodiment, a semiconductor light emitting device includes first and second electrodes, first and second semiconductor layers and a light emitting layer. The first electrode includes a first region, a second region, and a third region provided between them. The first semiconductor layer includes a first portion on the first region and a second portion on the second region. The light emitting layer includes a third portion on the first portion and a fourth portion on the second portion. The second semiconductor layer includes a fifth portion on the third portion and a sixth portion on the fourth portion. The insulating layer is provided between the first and second portions on the third region and between the third and fourth portions. The second electrode includes a seventh portion provided on the insulating layer, eighth and ninth portions contacting side surfaces of the fifth and sixth portions.Type: GrantFiled: December 26, 2012Date of Patent: August 26, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Jumpei Tajima, Kotaro Zaima, Hiroshi Ono, Shinji Yamada, Shigeya Kimura, Naoharu Sugiyama, Shinya Nunoue
-
Publication number: 20140231824Abstract: According to one embodiment, a nitride semiconductor device includes a foundation layer and a functional layer. The foundation layer is formed on an Al-containing nitride semiconductor layer formed on a silicon substrate. The foundation layer has a thickness not less than 1 micrometer and including GaN. The functional layer is provided on the foundation layer. The functional layer includes a first semiconductor layer. The first semiconductor layer has an impurity concentration higher than an impurity concentration in the foundation layer and includes GaN of a first conductivity type.Type: ApplicationFiled: April 28, 2014Publication date: August 21, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: TOMONARI SHIODA, HUNG HUNG, JONGIL HWANG, TAISUKE SATO, NAOHARU SUGIYAMA, SHINYA NUNOUE
-
Patent number: 8809085Abstract: According to one embodiment, a method is disclosed for manufacturing a nitride semiconductor device. The method can include removing a growth substrate from a structure body by using a first treatment material. The structure body has the growth substrate, a buffer layer formed on the growth substrate, and the nitride semiconductor layer formed on the buffer layer. A support substrate is bonded to the nitride semiconductor layer. The method can include reducing thicknesses of the buffer layer and the nitride semiconductor layer by using a second treatment material different from the first treatment material after removing the growth substrate.Type: GrantFiled: August 31, 2011Date of Patent: August 19, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Taisuke Sato, Naoharu Sugiyama, Tomonari Shioda, Toshiki Hikosaka, Shinya Nunoue