Patents by Inventor Naohiro Mashino
Naohiro Mashino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240047329Abstract: A semiconductor device includes a first inorganic insulating layer, a metal post embedded in the first inorganic insulating layer, a semiconductor chip mounting part stacked on the first inorganic insulating layer, and a second inorganic insulating layer. The metal post has first and second end faces that are exposed in the first and second opposite surfaces, respectively, of the first inorganic insulating layer. The semiconductor chip mounting part has first and second opposite surfaces and a side surface connecting the first and second opposite surfaces of the semiconductor chip mounting part. The first surface of the semiconductor chip mounting part contacts the second surface of the first inorganic insulating layer. The second inorganic insulating layer covers the entirety of the second surface and the entirety of the side surface of the semiconductor chip mounting part. The second inorganic insulating layer is continuous with the first inorganic insulating layer.Type: ApplicationFiled: July 24, 2023Publication date: February 8, 2024Inventor: Naohiro MASHINO
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Patent number: 11659667Abstract: A wiring board includes an insulating layer; an insulating oxide film that is formed by forming a film of metal oxide or semimetal oxide on a surface of the insulating layer; a seed layer that is made of metal and that is stacked on the insulating oxide film; and an electrode that is made of metal and that is formed on the seed layer, wherein the insulating oxide film and the seed layer are removed from an area not overlapping the electrode to expose the insulating layer.Type: GrantFiled: July 21, 2021Date of Patent: May 23, 2023Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventor: Naohiro Mashino
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Publication number: 20220046800Abstract: A wiring board includes an insulating layer; an insulating oxide film that is formed by forming a film of metal oxide or semimetal oxide on a surface of the insulating layer; a seed layer that is made of metal and that is stacked on the insulating oxide film; and an electrode that is made of metal and that is formed on the seed layer, wherein the insulating oxide film and the seed layer are removed from an area not overlapping the electrode to expose the insulating layer.Type: ApplicationFiled: July 21, 2021Publication date: February 10, 2022Inventor: Naohiro Mashino
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Patent number: 8179689Abstract: A printed circuit board has capacitors, a grounding wiring pattern having a bonding surface on which a semiconductor device is bonded, and a contact surface located opposite from the bonding surface thereof and coupled to first electrodes of the capacitors, and a power supply wiring pattern having a bonding surface on which the semiconductor device is bonded, and a contact surface located opposite from the bonding surface thereof and coupled to second electrodes of the capacitors. The grounding and power supply wiring patterns are alternately arranged in a predetermined direction, and the capacitors are coupled in parallel with respect to the grounding and power supply wiring patterns.Type: GrantFiled: May 20, 2009Date of Patent: May 15, 2012Assignee: Shinko Electric Industries Co., Ltd.Inventor: Naohiro Mashino
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Patent number: 8101461Abstract: A method of manufacturing a semiconductor device includes: (a) half-dicing a semiconductor wafer including plural semiconductor chips, thereby forming dicing grooves in the semiconductor wafer, wherein each semiconductor chip includes a circuit and pads and wherein the semiconductor wafer includes: a first surface on which the circuit and the pads are formed; and a second surface opposite to the first surface, (b) connecting the pads to each other by conductive connectors; (c) sealing the first surface of the semiconductor wafer, the dicing grooves and the conductive connectors with a resin; (d) grinding the second surface of the semiconductor wafer, thereby forming a group of sealed chips; (e) dividing the group of sealed chips into individual sealed chips; (f) mounting and stacking the individual sealed chips on a wiring substrate having connection terminals thereon; and (g) electrically-connecting the conductive connectors and the connection terminals using a conductive member.Type: GrantFiled: December 15, 2009Date of Patent: January 24, 2012Assignee: Shinko Electric Industries Co., Ltd.Inventors: Akihito Takano, Naohiro Mashino
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Patent number: 8007649Abstract: A plasma treatment is performed on the surface of one side of a polyimide film made of a resin. When wettability is imparted to the surface of the one side of the polyimide film, the plasma treatment is performed on the surface of the one side of the polyimide film to which sprayed water adhere.Type: GrantFiled: February 3, 2005Date of Patent: August 30, 2011Assignee: Shinko Electric Industries Co., Ltd.Inventor: Naohiro Mashino
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Patent number: 8004382Abstract: An inductor device includes a first magnetic body pattern layer in which slits are provided and which is made to a pattern, a lower insulating layer formed on the first magnetic body pattern layer, a planar coil layer formed on the lower insulating layer, an upper insulating layer formed on the planar coil layer, and a second magnetic body pattern layer formed on the upper insulating layer and in which slits are provided and which is made to a pattern, wherein the first magnetic body pattern layer and the second magnetic body pattern layer are arranged to intersect orthogonally with the planar coil layer.Type: GrantFiled: February 19, 2010Date of Patent: August 23, 2011Assignee: Shinko Electric Industries Co., Ltd.Inventor: Naohiro Mashino
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Patent number: 7936568Abstract: A capacitor built-in substrate of the present invention includes; a base resin layer; a plurality of capacitors arranged side by side in a lateral direction in a state that the capacitors are passed through the base resin layer, each of the capacitors constructed by a first electrode provided to pass through the base resin layer and having projection portions projected from both surface sides of the base resin layer respectively such that the projection portion on one surface side of the base resin layer serves as a connection portion, a dielectric layer for covering the projection portion of the first electrode on other surface side of the base resin layer, and a second electrode for covering the dielectric layer; a through electrode provided to pass through the base resin layer and having projection portions projected from both surface sides of the base resin layer respectively; and a built-up wiring formed on the other surface side of the base resin layer and connected to the second electrodes of the capacType: GrantFiled: August 3, 2007Date of Patent: May 3, 2011Assignee: Shinko Electric Industries Co., Ltd.Inventor: Naohiro Mashino
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Patent number: 7929320Abstract: There is provided a wiring board having a shield function. The wiring board includes: a plurality of conductive shield patterns adapted to surround a circumference of at least one electronic component mounting area on the wiring board, the plurality of conductive shield patterns being adjacent to each other; and at least one inductor formed of a conductive pattern and provided between the conductive shield patterns.Type: GrantFiled: July 1, 2008Date of Patent: April 19, 2011Assignee: Shinko Electric Industries Co., Ltd.Inventor: Naohiro Mashino
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Patent number: 7909976Abstract: It is characterized in that in the case of filling a through hole formed in a substrate with a plated metal by electrolytic plating, the electrolytic plating is started by a high current density higher than Constant Current Density capable of fully filling the through hole when the electrolytic plating is performed with a current density held constant as a current density of the electrolytic plating, and the electrolytic plating is continued by being changed to a current density lower than the high current density by the time of reaching formation of a seam diameter in which an inside diameter does not decrease even when the electrolytic plating is continued after the electrolytic plating at the high current density is started.Type: GrantFiled: December 27, 2006Date of Patent: March 22, 2011Assignee: Shinko Electric Industries Co., Ltd.Inventor: Naohiro Mashino
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Publication number: 20100231344Abstract: An inductor device includes a first magnetic body pattern layer in which slits are provided and which is made to a pattern, a lower insulating layer formed on the first magnetic body pattern layer, a planar coil layer formed on the lower insulating layer, an upper insulating layer formed on the planar coil layer, and a second magnetic body pattern layer formed on the upper insulating layer and in which slits are provided and which is made to a pattern, wherein the first magnetic body pattern layer and the second magnetic body pattern layer are arranged to intersect orthogonally with the planar coil layer.Type: ApplicationFiled: February 19, 2010Publication date: September 16, 2010Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventor: Naohiro MASHINO
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Patent number: 7755910Abstract: A capacitor built-in interposer of the present invention, includes a base resin layer, a capacitor first electrode provided to pass through the base resin layer and having projection portions projected from both surface sides of the base resin layer respectively whereby the projection portion on one surface side of the base resin layer serves as a connection portion, a capacitor dielectric layer for covering the projection portion of the first electrode on other surface side of the base resin layer, and a capacitor second electrode for covering the dielectric layer, wherein a plurality of capacitors each constructed by the first electrode, the dielectric layer, and the second electrode are arranged and aligned in a lateral direction in a state that the capacitors are passed through the base resin layer.Type: GrantFiled: August 3, 2007Date of Patent: July 13, 2010Assignee: Shinko Electric Industries Co., Ltd.Inventor: Naohiro Mashino
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Publication number: 20100148340Abstract: A method of manufacturing a semiconductor device includes: (a) half-dicing a semiconductor wafer including plural semiconductor chips, thereby forming dicing grooves in the semiconductor wafer, wherein each semiconductor chip includes a circuit and pads and wherein the semiconductor wafer includes: a first surface on which the circuit and the pads are formed; and a second surface opposite to the first surface, (b) connecting the pads to each other by conductive connectors; (c) sealing the first surface of the semiconductor wafer, the dicing grooves and the conductive connectors with a resin; (d) grinding the second surface of the semiconductor wafer, thereby forming a group of sealed chips; (e) dividing the group of sealed chips into individual sealed chips; (f) mounting and stacking the individual sealed chips on a wiring substrate having connection terminals thereon; and (g) electrically-connecting the conductive connectors and the connection terminals using a conductive member.Type: ApplicationFiled: December 15, 2009Publication date: June 17, 2010Applicant: Shinko Electric Industries Co., Ltd.Inventors: Akihito TAKANO, Naohiro Mashino
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Patent number: 7655504Abstract: Two semiconductor substrates are first bonded together by means of a metal bump, while respective one-side surfaces on which device patterns are formed are faced each other, and a resin is then filled into a gap between the respective one-side surfaces and thereafter each of the semiconductor substrates is polished and thinned to a prescribed thickness. Furthermore, a via hole and an insulating film are formed; part of a portion in contact with the metal bump, of the insulating film, is opened; the inside of the via hole is filled with a conductor; and an electrode pad is formed on the conductor, to thereby form structures. Finally, a required number of structures are electrically connected with each other through the electrode pad and stacked to thereby obtain a semiconductor device.Type: GrantFiled: May 16, 2008Date of Patent: February 2, 2010Assignee: Shinko Electric Industries Co., Ltd.Inventor: Naohiro Mashino
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Publication number: 20090290317Abstract: A printed circuit board has capacitors, a grounding wiring pattern having a bonding surface on which a semiconductor device is bonded, and a contact surface located opposite from the bonding surface thereof and coupled to first electrodes of the capacitors, and a power supply wiring pattern having a bonding surface on which the semiconductor device is bonded, and a contact surface located opposite from the bonding surface thereof and coupled to second electrodes of the capacitors. The grounding and power supply wiring patterns are alternately arranged in a predetermined direction, and the capacitors are coupled in parallel with respect to the grounding and power supply wiring patterns.Type: ApplicationFiled: May 20, 2009Publication date: November 26, 2009Inventor: Naohiro MASHINO
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Publication number: 20090243035Abstract: In a semiconductor device that is formed by joining two semiconductor elements together to oppose device layers to each other, inductor patterns for transmitting and receiving a signal and feeding a power and bumps for connecting electrically the semiconductor elements and for supporting the inductor patterns and the semiconductor elements being arranged opposedly in an electrically isolated state are provided on a surface of the device layer of at least one of semiconductor elements and an electrically insulating material is filled in a space between opposing surfaces of the semiconductor elements.Type: ApplicationFiled: March 23, 2009Publication date: October 1, 2009Applicant: Shinko Electric Industries Co., Ltd.Inventor: Naohiro MASHINO
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Patent number: 7530163Abstract: There is provided a electronic parts packaging structure that includes a mounted body on which an electronic parts is mounted, the electronic parts having a connection pad, which has an etching stopper film (a copper film, a gold film, a silver film, or a conductive past film) as an uppermost film, and mounted on the mounted body to direct the connection pad upward, an interlayer insulating film for covering the electronic parts, a via hole formed in the insulating film on the connection pad of the electronic parts, and a wiring pattern connected to the connection pad via the via hole.Type: GrantFiled: November 23, 2005Date of Patent: May 12, 2009Assignee: Shinko Electric Industries Co., Ltd.Inventors: Masahiro Sunohara, Kei Murayama, Naohiro Mashino, Mitsutoshi Higashi
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Publication number: 20090008148Abstract: There is provided a wiring board having a shield function. The wiring board includes: a plurality of conductive shield patterns adapted to surround a circumference of at least one electronic component mounting area on the wiring board, the plurality of conductive shield patterns being adjacent to each other; and at least one inductor formed of a conductive pattern and provided between the conductive shield patterns.Type: ApplicationFiled: July 1, 2008Publication date: January 8, 2009Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventor: Naohiro Mashino
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Publication number: 20080291649Abstract: A capacitor built-in substrate of the present invention includes; a base resin layer; a plurality of capacitors arranged side by side in a lateral direction in a state that the capacitors are passed through the base resin layer, each of the capacitors constructed by a first electrode provided to pass through the base resin layer and having projection portions projected from both surface sides of the base resin layer respectively such that the projection portion on one surface side of the base resin layer serves as a connection portion, a dielectric layer for covering the projection portion of the first electrode on other surface side of the base resin layer, and a second electrode for covering the dielectric layer; a through electrode provided to pass through the base resin layer and having projection portions projected from both surface sides of the base resin layer respectively; and a built-up wiring formed on the other surface side of the base resin layer and connected to the second electrodes of the capacType: ApplicationFiled: August 3, 2007Publication date: November 27, 2008Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventor: Naohiro Mashino
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Publication number: 20080233677Abstract: Two semiconductor substrates are first bonded together by means of a metal bump, while respective one-side surfaces on which device patterns are formed are faced each other, and a resin is then filled into a gap between the respective one-side surfaces and thereafter each of the semiconductor substrates is polished and thinned to a prescribed thickness. Furthermore, a via hole and an insulating film are formed; part of a portion in contact with the metal bump, of the insulating film, is opened; the inside of the via hole is filled with a conductor; and an electrode pad is formed on the conductor, to thereby form structures. Finally, a required number of structures are electrically connected with each other through the electrode pad and stacked to thereby obtain a semiconductor device.Type: ApplicationFiled: May 16, 2008Publication date: September 25, 2008Applicant: Shinko Electric Industries Co., Ltd.Inventor: Naohiro Mashino