Patents by Inventor Naohiro Matsui
Naohiro Matsui has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10367660Abstract: A rate determination apparatus 1 includes a reception unit 2 configured to receive a transmission frame modulated by an FSK modulation scheme, a symbol rate detection unit 3 configured to detect a symbol rate based on a period of a preamble portion in the received transmission frame, a multilevel symbol detection unit 4 configured to detect a multilevel-modulated multilevel symbol based on a frequency deviation in the received transmission frame, and a bit rate determination unit 5 configured to determine a bit rate based on the detected symbol rate and the detected multilevel symbol. Then, the bit rate can be determined during communication.Type: GrantFiled: November 2, 2017Date of Patent: July 30, 2019Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Kichung Kim, Hiroyuki Okada, Naohiro Matsui, Tomoaki Hirota
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Publication number: 20190199556Abstract: A receiving device performs, in an equalization processing circuit that performs an equalizing process for a received signal sequence and outputs a sequence to be demodulated, a first transmission-path estimating process of generating a first compensation coefficient indicating a propagation coefficient of a transmission path of a received signal, based on a preamble sequence, a second transmission-path estimating process of generating a second compensation coefficient from a received header-replica sequence generated by performing demodulation and modulation for a header sequence included in a first equalizer-compensated output sequence in which distortion has been compensated based on the first compensation coefficient, a third transmission-path estimating process of generating a third compensation coefficient by synthesizing the first and second compensation coefficients with each other, and a propagation-path compensating process of performing a distortion compensating process for a payload sequence incluType: ApplicationFiled: November 16, 2018Publication date: June 27, 2019Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Takahiro SATO, Naohiro MATSUI
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Patent number: 10263654Abstract: A radio frequency signal can be received in an intermediate frequency mode suitable for radio wave reception conditions. An oscillator has a variable oscillation frequency. A quadrature demodulator includes a frequency mixer and generates an intermediate frequency signal having an intermediate frequency lower than the frequency of the radio frequency signal. An ADC receives the intermediate frequency signal passed through an analog filter and converts the received intermediate frequency signal to a digital signal. A channel selection signal processing section generates a demodulated signal from the intermediate frequency signal converted to the digital signal. A mode control section switches the operating mode of the quadrature demodulator between a zero intermediate frequency mode and a low intermediate frequency mode in accordance with the radio wave reception conditions.Type: GrantFiled: February 6, 2018Date of Patent: April 16, 2019Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Naohiro Matsui, Hiroyuki Okada, Kichung Kim, Tomoaki Hirota, Takahiro Sato, Osamu Inagawa
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Publication number: 20180294828Abstract: A radio frequency signal can be received in an intermediate frequency mode suitable for radio wave reception conditions. An oscillator has a variable oscillation frequency. A quadrature demodulator includes a frequency mixer and generates an intermediate frequency signal having an intermediate frequency lower than the frequency of the radio frequency signal. An ADC receives the intermediate frequency signal passed through an analog filter and converts the received intermediate frequency signal to a digital signal. A channel selection signal processing section generates a demodulated signal from the intermediate frequency signal converted to the digital signal. A mode control section switches the operating mode of the quadrature demodulator between a zero intermediate frequency mode and a low intermediate frequency mode in accordance with the radio wave reception conditions.Type: ApplicationFiled: February 6, 2018Publication date: October 11, 2018Inventors: Naohiro MATSUI, Hiroyuki Okada, Kichung Kim, Tomoaki Hirota, Takahiro Sato, Osamu Inagawa
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Publication number: 20180167238Abstract: A rate determination apparatus 1 includes a reception unit 2 configured to receive a transmission frame modulated by an FSK modulation scheme, a symbol rate detection unit 3 configured to detect a symbol rate based on a period of a preamble portion in the received transmission frame, a multilevel symbol detection unit 4 configured to detect a multilevel-modulated multilevel symbol based on a frequency deviation in the received transmission frame, and a bit rate determination unit 5 configured to determine a bit rate based on the detected symbol rate and the detected multilevel symbol. Then, the bit rate can be determined during communication.Type: ApplicationFiled: November 2, 2017Publication date: June 14, 2018Applicant: Renesas Electronics CorporationInventors: Kichung KIM, Hiroyuki OKADA, Naohiro MATSUI, Tomoaki HIROTA
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Patent number: 9621116Abstract: According to one embodiment, there is provided an active load circuit including a first transistor, a second transistor, a first resistor, a second resistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and a line. The third transistor is placed between the first transistor and the first reference node. The fourth transistor is placed between the second transistor and the first reference node. The seventh transistor is placed between the fifth transistor and the first reference node. The eighth transistor is placed between the sixth transistor and the first reference node. A line connecting a fifth node between the fifth transistor and the seventh transistor and a sixth node between the sixth transistor and the eighth transistor.Type: GrantFiled: September 3, 2015Date of Patent: April 11, 2017Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Rui Ito, Naohiro Matsui
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Publication number: 20160268977Abstract: According to one embodiment, there is provided an active load circuit including a first transistor, a second transistor, a first resistor, a second resistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and a line. The third transistor is placed between the first transistor and the first reference node. The fourth transistor is placed between the second transistor and the first reference node. The seventh transistor is placed between the fifth transistor and the first reference node. The eighth transistor is placed between the sixth transistor and the first reference node. a line connecting a fifth node between the fifth transistor and the seventh transistor and a sixth node between the sixth transistor and the eighth transistor.Type: ApplicationFiled: September 3, 2015Publication date: September 15, 2016Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Rui ITO, Naohiro MATSUI
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Patent number: 9281792Abstract: An RFVGA variably controls a gain according to an RFVGA gain control signal and amplifies and outputs a reception signal. A low-pass filter filters a signal output from a frequency converter. An OFDM demodulator generates a digital signal based on an output signal from the low-pass filter. A power detection evaluation circuit controls the RFVGA gain control signal based on a voltage value (DET0) of the RFVGA gain control signal or a voltage value (DET1) of the output signal from the RFVGA, and a voltage value (DET3) of an output signal from the low-pass filter and a voltage value (DET2) of an intermediate node of the low-pass filter.Type: GrantFiled: September 16, 2014Date of Patent: March 8, 2016Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Naohiro Matsui
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Publication number: 20150117571Abstract: An RFVGA variably controls a gain according to an RFVGA gain control signal and amplifies and outputs a reception signal. A low-pass filter filters a signal output from a frequency converter. An OFDM demodulator generates a digital signal based on an output signal from the low-pass filter. A power detection evaluation circuit controls the RFVGA gain control signal based on a voltage value (DET0) of the RFVGA gain control signal or a voltage value (DET1) of the output signal from the RFVGA, and a voltage value (DET3) of an output signal from the low-pass filter and a voltage value (DET2) of an intermediate node of the low-pass filter.Type: ApplicationFiled: September 16, 2014Publication date: April 30, 2015Inventor: Naohiro MATSUI
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Patent number: 8478215Abstract: A harmonic rejection mixer converts a frequency of a radio frequency signal by using a first to a third local signals (LOs) whose phases are different from each other, and the harmonic rejection mixer includes a phase difference detection circuit for detecting a phase difference between the first LO and the second LO, a phase difference detection circuit for detecting a phase difference between the first LO and the third LO, a phase adjustment circuit for adjusting the phase of the second LO so that the phase difference detected by the phase difference detection circuit becomes a first phase difference, and a phase adjustment circuit for adjusting the phase of the third LO so that the phase difference detected by the phase difference detection circuit becomes a second phase difference. It is thereby possible to achieve high precision harmonic rejection characteristics.Type: GrantFiled: July 15, 2011Date of Patent: July 2, 2013Assignee: Renesas Electronics CorporationInventor: Naohiro Matsui
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Publication number: 20120200440Abstract: An A/D converter and a semiconductor device simple in configuration are provided which can keep a constant noise shaping characteristic without depending on manufacturing variations or a temperature change. A semiconductor device includes a delta-sigma modulator, an input changeover switch, and a control logic circuit. The delta-sigma modulator can change a time constant of an internal circuit according to a control signal. The input changeover switch selectively inputs any one of an input amplitude voltage and a reference voltage to the delta-sigma modulator. A control logic circuit is coupled to an output of the delta-sigma modulator, and generates the control signal.Type: ApplicationFiled: January 26, 2012Publication date: August 9, 2012Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Hiroyuki OKADA, Naohiro MATSUI
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Publication number: 20120064850Abstract: A harmonic rejection mixer converts a frequency of a radio frequency signal by using a first to a third local signals (LOs) whose phases are different from each other, and the harmonic rejection mixer includes a phase difference detection circuit for detecting a phase difference between the first LO and the second LO, a phase difference detection circuit for detecting a phase difference between the first LO and the third LO, a phase adjustment circuit for adjusting the phase of the second LO so that the phase difference detected by the phase difference detection circuit becomes a first phase difference, and a phase adjustment circuit for adjusting the phase of the third LO so that the phase difference detected by the phase difference detection circuit becomes a second phase difference. It is thereby possible to achieve high precision harmonic rejection characteristics.Type: ApplicationFiled: July 15, 2011Publication date: March 15, 2012Applicant: Renesas Electronics CorporationInventor: Naohiro Matsui
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Patent number: 7898328Abstract: In a wireless communications system, it is important to realize a limiter operation by which a differential amplifier for amplifying a local signal may stably supply an output signal having a constant amplitude. However, when a signal handled by the system has a high frequency, a gain of the differential amplifier is reduced and the limiter operation may not be performed appropriately. The differential amplifier is configured employing a double cascode connection to enhance an output impedance, an upper transistor of the double cascode connection realizes enhancement in gain and frequency characteristics based on a positive feedback signal, and a lower transistor of the double cascode connection controls an operating point and suppresses an allowable output voltage range by operating in a linear region and based on a negative feedback signal to facilitate the limiter operation.Type: GrantFiled: December 4, 2009Date of Patent: March 1, 2011Assignee: Renesas Electronics CorporationInventor: Naohiro Matsui
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Publication number: 20100148868Abstract: In a wireless communications system, it is important to realize a limiter operation by which a differential amplifier for amplifying a local signal may stably supply an output signal having a constant amplitude. However, when a signal handled by the system has a high frequency, a gain of the differential amplifier is reduced and the limiter operation may not be performed appropriately. The differential amplifier is configured employing a double cascode connection to enhance an output impedance, an upper transistor of the double cascode connection realizes enhancement in gain and frequency characteristics based on a positive feedback signal, and a lower transistor of the double cascode connection controls an operating point and suppresses an allowable output voltage range by operating in a linear region and based on a negative feedback signal to facilitate the limiter operation.Type: ApplicationFiled: December 4, 2009Publication date: June 17, 2010Applicant: NEC ELECTRONICS CORPORATIONInventor: Naohiro Matsui
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Patent number: 7696789Abstract: Disclosed is a high-frequency signal detector circuit including a diode detector circuit for detecting an input signal by diode detection; a differential-input/differential output amplifier with a common mode feedback circuit, the amplifier including a differential amplifying circuit for differentially receiving outputs of the diode detector circuit and outputting a differential output signal, and a common mode feedback circuit for controlling the differential amplifying circuit in such a manner that a voltage corresponding to a mid-point of the differential output signal from the differential amplifying circuit will take on a voltage identical with a prescribed voltage; and a differential-input/single-ended output amplifier for receiving the differential output signal of the differential amplifying circuit and outputting a single-ended output signal.Type: GrantFiled: May 23, 2008Date of Patent: April 13, 2010Assignee: NEC Electronics CorporationInventor: Naohiro Matsui
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Patent number: 7649418Abstract: There is provided a variable-gain amplifier, including two cascode amplifiers and an attenuator. The cascode amplifiers are mutually connected in parallel via the attenuator.Type: GrantFiled: June 11, 2007Date of Patent: January 19, 2010Assignee: NEC Electronics CorporationInventor: Naohiro Matsui
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Publication number: 20090021282Abstract: Disclosed is a high-frequency signal detector circuit including a diode detector circuit for detecting an input signal by diode detection; a differential-input/differential output amplifier with a common mode feedback circuit, the amplifier including a differential amplifying circuit for differentially receiving outputs of the diode detector circuit and outputting a differential output signal, and a common mode feedback circuit for controlling the differential amplifying circuit in such a manner that a voltage corresponding to a mid-point of the differential output signal from the differential amplifying circuit will take on a voltage identical with a prescribed voltage; and a differential-input/single-ended output amplifier for receiving the differential output signal of the differential amplifying circuit and outputting a single-ended output signal.Type: ApplicationFiled: May 23, 2008Publication date: January 22, 2009Applicant: NEC ELECTRONICS CORPOPRATIONInventor: Naohiro Matsui
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Patent number: 7456692Abstract: A gain variable amplifier according to an embodiment of the present invention includes: an amplifier circuit amplifying an input signal with a variable gain; and a gain control circuit controlling the gain of the amplifier circuit based on a gain control signal, in which the amplifier circuit includes: an amplifying element amplifying the input signal; an output element series-connected with the amplifying element and outputting a signal amplified with the amplifying element; and a bias circuit changing a potential at a node between the output element and the amplifying element based on the gain control of the gain control circuit.Type: GrantFiled: January 30, 2006Date of Patent: November 25, 2008Assignee: NEC Electronics CorporationInventors: Tatsuhiko Maruyama, Naohiro Matsui
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Publication number: 20070296501Abstract: There is provided a variable-gain amplifier, including two cascode amplifiers and an attenuator. The cascode amplifiers are mutually connected in parallel via the attenuator.Type: ApplicationFiled: June 11, 2007Publication date: December 27, 2007Applicant: NEC ELECTRONICS CORPORATIONInventor: Naohiro MATSUI
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Publication number: 20060170497Abstract: A gain variable amplifier according to an embodiment of the present invention includes: an amplifier circuit amplifying an input signal with a variable gain; and a gain control circuit controlling the gain of the amplifier circuit based on a gain control signal, in which the amplifier circuit includes: an amplifying element amplifying the input signal; an output element series-connected with the amplifying element and outputting a signal amplified with the amplifying element; and a bias circuit changing a potential at a node between the output element and the amplifying element based on the gain control of the gain control circuit.Type: ApplicationFiled: January 30, 2006Publication date: August 3, 2006Applicant: NEC COMPOUND SEMICONDUCTOR DEVICES, LTD.Inventors: Tatsuhiko Maruyama, Naohiro Matsui