Abstract: A binary FSK modulator circuit is composed of a signal mapping circuit, a D/A converter circuit, and a quadrature modulator circuit. The signal mapping circuit generates I data and Q data through signal mapping in response to an input bit stream, the I data being representative of an I channel projection and the Q data being representative of a Q channel projection. The D/A converter circuit develops an I-channel signal and a Q-channel signal through implementing D/A conversion on the I data and the Q data, respectively. The quadrature modulator circuit develops a resultant FSK-modulated signal through quadrature modulation of the I-channel signal and the Q-channel signal on a carrier signal.

Abstract: BPF having a band width of |reference signal fREF-mixer output signal fMIX OUT| is connected to a phase comparator. When an output signal corresponding to the passage of this band width has been obtained, a changeover switch is turned OFF. Upon detection such that the PLL circuit is unlockable, an output signal is obtained from an offset differential pair circuit, the changeover switch is turned ON, and the time constant of LPF is reduced to shorten the lock-up time, and the voltage applied to VCO is made larger than the usual voltage. By virtue of this construction, a PLL circuit of an analog system can be realized which can shorten the lock-up time and, in addition, can reduce noise and spurious harmonics.

Abstract: BPF having a band width of |reference signal fREF−mixer output signal fMIX OUT| is connected to a phase comparator. When an output signal corresponding to the passage of this band width has been obtained, a changeover switch is turned OFF. Upon detection such that the PLL circuit is unlockable, an output signal is obtained from an offset differential pair circuit, the changeover switch is turned ON, and the time constant of LPF is reduced to shorten the lock-up time, and the voltage applied to VCO is made larger than the usual voltage. By virtue of this construction, a PLL circuit of an analog system can be realized which can shorten the lock-up time and, in addition, can reduce noise and harmonic spurious.

Abstract: The present invention provides a phase comparator provided in a phase locked loop circuit, the phase comparator converting a phase difference between first and second input signals into a current signal, wherein the phase comparator has: a lock detector for detecting locked and unlocked states of the phase locked loop circuit to generate a detected signal which indicates one of the locked and unlocked states; and a current source connected to the lock detector for receiving the detected signal from the lock detector and varying a supply current based on the detected signal, so that if the detected signal indicates the unlocked states, then the current source increases the supplying current.

Abstract: A phase-comparison circuit includes (a) a first PNP transistor, (b) a second PNP transistor, (c) a third NPN transistor electrically connected to both a collector of the first PNP transistor and a base of the second PNP transistor, and (d) a constant current source electrically connected to an emitter of the third NPN transistor. The phase comparison circuit compensates for an offset current between a reference current and an output current, and as a result, can properly operate at a low voltage.