Abstract: The object of the present invention is to propose an etch channel sealing structure characterized by excellent impermeability to moisture and resistance to temporal change of the diaphragm in the pressure sensor produced according to the sacrificial layer etching technique, and to provide a pressure sensor characterized by excellent productivity and durability. After a very small gap is formed by the sacrificial layer etching technique, silicon oxide film is deposited by the CVD technique or the like, there by sealing the etch channel. Further, impermeable thin film of polysilicon or the like is formed to cover the oxide film. This allows an etch channel sealing structure to be simplified in the pressure sensor produced according to the sacrificial layer etching technique, and prevents entry of moisture into the cavity, thereby improving moisture resistance. Moreover, sealing material with small film stress reduces temporal deformation of the diaphragm.

Abstract: The object of the present invention is to propose an etch channel sealing structure characterized by excellent impermeability to moisture and resistance to temporal change of the diaphragm in the pressure sensor produced according to the sacrificial layer etching technique, and to provide a pressure sensor characterized by excellent productivity and durability. After a very small gap is formed by the sacrificial layer etching technique, silicon oxide film is deposited by the CVD technique or the like, thereby sealing the etch channel. Further, impermeable thin film of polysilicon or the like is formed to cover the oxide film. This allows an etch channel sealing structure to be simplified in the pressure sensor produced according to the sacrificial layer etching technique, and prevents entry of moisture into the cavity, thereby improving moisture resistance. Moreover, sealing material with small film stress reduces temporal deformation of the diaphragm.

Abstract: According to the invention, there is provided a water cooled inverter structure forming a plurality of shallow cavities and deep cavities in a housing, fixing a bottom surface of power semiconductor modules to shallow cavities to form a shallow water channel and directly cooling the power semiconductor modules using this shallow water channel. Since cooling water flows fast in the shallow water channel, it is possible to improve a cooling efficiency and also reduce pressure loss using a deep water channel with deep cavities. Furthermore, providing a plurality of cavities makes it possible to reduce a size of the power semiconductor modules and provide a plurality of power semiconductor modules, thus improving reliability. It is possible to place a control board below the water channel to thermally cut off the control board from the power semiconductor modules, which makes it possible to reduce temperature of a control circuit.

Abstract: According to the invention, there is provided a water cooled inverter structure forming a plurality of shallow cavities and deep cavities in a housing, fixing a bottom surface of power semiconductor modules to shallow cavities to form a shallow water channel and directly cooling the power semiconductor modules using this shallow water channel. Since cooling water flows fast in the shallow water channel, it is possible to improve a cooling efficiency and also reduce pressure loss using a deep water channel with deep cavities. Furthermore, providing a plurality of cavities makes it possible to reduce a size of the power semiconductor modules and provide a plurality of power semiconductor modules, thus improving reliability. It is possible to place a control board below the water channel to thermally cut off the control board from the power semiconductor modules, which makes it possible to reduce temperature of a control circuit.

Abstract: According to the invention, there is provided a water cooled inverter structure forming a plurality of shallow cavities and deep cavities in a housing, fixing a bottom surface of power semiconductor modules to shallow cavities to form a shallow water channel and directly cooling the power semiconductor modules using this shallow water channel. Since cooling water flows fast in the shallow water channel, it is possible to improve a cooling efficiency and also reduce pressure loss using a deep water channel with deep cavities. Furthermore, providing a plurality of cavities makes it possible to reduce a size of the power semiconductor modules and provide a plurality of power semiconductor modules, thus improving reliability. It is possible to place a control board below the water channel to thermally cut off the control board from the power semiconductor modules, which makes it possible to reduce temperature of a control circuit.

Abstract: According to the invention, there is provided a water cooled inverter structure forming a plurality of shallow cavities and deep cavities in a housing, fixing a bottom surface of power semiconductor modules to shallow cavities to form a shallow water channel and directly cooling the power semiconductor modules using this shallow water channel. Since cooling water flows fast in the shallow water channel, it is possible to improve a cooling efficiency and also reduce pressure loss using a deep water channel with deep cavities. Furthermore, providing a plurality of cavities makes it possible to reduce a size of the power semiconductor modules and provide a plurality of power semiconductor modules, thus improving reliability. It is possible to place a control board below the water channel to thermally cut off the control board from the power semiconductor modules, which makes it possible to reduce temperature of a control circuit.

Abstract: A semiconductor module has a plurality of power semiconductor devices mounted on a substrate, and a metal foil for wiring is mounted on the substrate so that an asymmetric unit arrangement of the semiconductor devices is formed. In the device, all of the units are arranged in the same direction on the substrate, and all of the units are electrically connected with electrode terminal feet, and the electrode terminal feet are electrically connected with linkage terminal foot. The electrode terminal feet are disposed with a certain interval.

Abstract: In a semiconductor device, such as a diode and thyristor, having at least one pn junction between a pair of main surfaces, a first main electrode formed on the surface of one of the main surfaces and a second main electrode formed on the surface of the other one of the main surfaces, a semiconductor lattice defect is formed such that its lattice defect density increases gradually in the direction from the first main electrode to the second main electrode. Since the distribution of the carrier density in the conduction state can be flattened, the reverse recovery charge can be reduced substantially without causing the ON-state voltage to increase.

Abstract: A semiconductor device has a well region formed in the surface of a substrate, and has functional portions such as MOSFET and bipolar transistor formed in the well region. The carrier concentration profile of the well region assumes the shape of a valley in the direction of depth thereof, and a minimum point thereof has a concentration of smaller than 5.times.10.sup.15 cm.sup.-3 and is located at a position within 1.6 .mu.m from the surface of the substrate. Preferably, the minimum point should have a concentration of greater than 5.times.10.sup.14 cm.sup.-3 but smaller than 5.times.10.sup.15 cm.sup.-3, and more preferably a concentration of greater than 1.times.10.sup.15 cm.sup.-3 but smaller than 5.times.10.sup.15 cm.sup.-3.

Abstract: A plasma treatment apparatus for forming a thin film on a substrate in a vacuum vessel includes a magnetic field generator which can be positioned inside or outside the vacuum vessel, and a microwave source. The magnetic field strength is controllable such that an electron cyclotron resonance (ECR) area is defined near the substrate. The magnetic field generator can be arranged so that plasma and reactive gas introduction ports are on the microwave introduction side of the ECR area and the substrate is on the opposite side of the ECR area. Alternatively, a gas introduction port can be positioned such that reactive gas is introduced into the ECR area or onto the substrate.

Abstract: TFTs with an inverted stagger structure are fabricated according to the invention as follows; a glass substrate after depositing amorphous silicon (a-Si) thereupon is transferred to a laser annealing chamber which is kept in non-oxidation ambient and provided with a sample holder and a substrate heating mechanism. The substrate is fixed on the sample holder, then subjected to laser annealing while being heated from the glass substrate side, thereby growing polycrystalline silicon having substantially improved crystallinity, on which a-Si is further deposited. According to this process of the invention, it is capable of forming TFTs having a higher mobility and a smaller leakage current in the periphery of the substrate, with addition of almost no changes to the process and device structures of conventional TFTs which constitute pixels, and even more the peripheral drive circuitry is capable of being integrated in the display substrate.

Abstract: A laminar structure comprising an organic material and an inorganic material; for example, a coating structure on an organic substrate comprising an organic material on which an inorganic film must be formed and a method of producing the structure, a structure which is suitable for increasing the reliability of an optical disk and a method of producing this, a wiring structure on an organic substrate comprising the organic material on which electric wiring must be formed and a method of producing this, and a structure suitable for increasing the reliability of a semiconductor integrated circuit device and a method of producing this.

Abstract: A semiconductor device has a well region formed in the surface of a substrate, and has semiconductor elements such as MOSFETs and bipolar transistors formed in the well region. The carrier concentration profile of the well region assumes the shape of a valley in the direction of depth thereof, and a minimum point thereof has a concentration of smaller than 5.times.10.sup.15 cm.sup.-3 and is located at a position within 1.6 .mu.m from the surface of the substrate. Preferably, the minimum point should have a concentration of greater than 5.times.10.sup.14 cm.sup.-3 but smaller than 5.times.10.sup.15 cm.sup.-3, and more preferably a concentration of greater than 1.times.10.sup.15 cm.sup.-3 but smaller than 5.times.10.sup.15 cm.sup.-3.

Abstract: Disclosed is a semiconductor device having a support region, an element-forming region (e.g., an epitaxial layer) and a buried layer between the support region and the element-forming region, with at least one of a MOS element and a bipolar element being formed in the element-forming region. The feature of the present invention resides in that atoms of at least one element selected from oxygen, nitrogen, carbon, argon, neon, krypton and helium is contained in a layer in at least one of the element-forming region and the buried layer, so as to suppress auto-doping of impurities from the buried layer into the element-forming region and suppress swelling of the buried layer.

Abstract: A semiconductor memory including two cross-coupled driver MOS transistors respectively having source and drain regions within a semiconductor substrate and each of the drain regions being in ohmic contact with the gate electrode of the other driver MOS transistor. The gate electrodes of the driver MOS transistors are formed in a first-level polycrystalline silicon (polysilicon) layer and the two transfer MOS transistors respectively have their source and drain regions formed in portions of a second-level polysilicon layer. The driver regions are formed so as to be independently brought into ohmic contact with the respective drain regions of the driver MOS transistors, and each of the transfer MOS transistors have a gate electrode effected in a third-level polysilicon layer which also defines a word line.

Abstract: The present invention relates to a process for producing ultra-pure water, an apparatus for producing said ultra-pure water and a process for using the ultra-pure water produced according to said process. More particularly, the present invention relates to a process for producing ultra-pure water which comprises boiling a raw water to vaporize off the volatile components from the raw water, subsequently generating steam from the water, contacting the steam with a hydrophobic, porous, gas-permeable and liquid-impermeable membrane to make the steam permeate the membrane, and then condensing the steam, as well as to an apparatus for producing said ultra-pure water and a process for using said ultra-pure water.

Abstract: A plasma operation apparatus utilizes plasma generated by a microwave cooperative with a magnetic field as to perform a surface operation on a specimen such as semiconductor substrates, such as, for example, thin film deposition, etching, sputtering and plasma oxidation. The apparatus particularly takes advantage of electron cyclotron resonance and is suitable for performing highly efficient and high-quality plasma operations.

Abstract: A monolithic complementary semiconductor device comprising n-type and p-type well regions separated by a dielectric isolation region extending from the surface into the substrate region. The well region includes a highly doped buried region which is located at the bottom of the well region and separates an active region in the well from the substrate region. The isolation region is deeper than the buried region. The well-to-well isolation is enhanced by the combination of the buried region and the deep dielectric isolation region. Packing density and the high speed operation can also be improved.

Abstract: A semiconductor device has a structure in which two semiconductor substrates are coupled to each other through a semiconductor oxide film and a metal silicide film, and a semiconductor element, for example, a bi-polar transistor is formed in the semiconductor substrate on the metal silicide film side, whereby a metal silicide layer having a high melting point is provided beneath one region of the bi-polar transistor for example, an n.sup.+ buried collector layer and in ohmic contact with the n.sup.+ buried collector layer. An electrical isolation between the adjacent semiconductor elements is made by an insulating layer.

Abstract: A monolithic complementary semiconductor device comprising n-type and p-type well regions separated by a dielectric isolation region extending from the surface into the substrate region. The well region includes a highly doped buried region which is located at the bottom of the well region and separates an active region in the wall from the substrate region. The isolation region is deeper than the buried region. The well-to-well isolation is enhanced by the combination of the buried region and the deep dielectric isolation region. Packing density and the high speed operation can also be improved.