Patents by Inventor Naohiro Momma

Naohiro Momma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4772927
    Abstract: The present invention relates to a semiconductor device including a MOS transistor which is formed with a source region, a drain region and a channel region by the use of polycrystalline silicon, and a method of manufacturing the semiconductor device. Ions of carbon, oxygen or/and nitrogen are introduced into a polycrystalline silicon layer over the whole area thereof, and restrain conductive ions in the source and drain regions from diffusing into the channel region.
    Type: Grant
    Filed: October 23, 1986
    Date of Patent: September 20, 1988
    Assignee: Hitachi, Ltd.
    Inventors: Ryuichi Saito, Naohiro Momma
  • Patent number: 4735916
    Abstract: A method of fabricating a semiconductor device includes the steps of: forming at least one first semiconductor region of a first conductivity type and at least one second semiconductor region of a second conductivity type in a main surface of a semiconductor layer of the first conductivity type; forming a three-layer film having a desired shape on each of the first and second semiconductor regions, the three-layer film being made up of a bottom layer which is a conductive film, an intermediate layer which is a silicon nitride film, and a top layer which is a polycrystalline silicon film doped with one of arsenic and phosphorus; forming a first insulating layer on the side wall of the three-layer film; forming a second polycrystalline silicon film on the whole surface, and diffusing one of arsenic and phosphorus from the first polycrystalline silicon film into the second polycrystalline silicon film; selectively etching off the first polycrystalline silicon film and that portion of the second polycrystalline s
    Type: Grant
    Filed: February 10, 1987
    Date of Patent: April 5, 1988
    Assignee: Hitachi, Ltd.
    Inventors: Hideo Homma, Yutaka Misawa, Naohiro Momma
  • Patent number: 4682199
    Abstract: In a high-voltage thyristor comprising a semiconductor body having contiguous pnpn four layers, and opposed anode and cathode electrodes and a gate electrode provided for the semiconductor body, one of p-base and n-base regions having an impurity concentration higher than the other has an impurity concentration which is no more than 8.times.10.sup.15 atoms/cm.sup.3 in the vicinity of a junction between the one base region and an adjacent emitter region and which has a gradually decreasing gradient toward the other contiguous base region. The one base region has a sheet resistance of 500 to 1500 ohms/.quadrature.. The realization of a high-voltage, large-diameter and large-current thyristor can be ensured.
    Type: Grant
    Filed: April 28, 1983
    Date of Patent: July 21, 1987
    Assignee: Hitachi, Ltd.
    Inventors: Tsutomu Yatsuo, Naohiro Momma, Masayoshi Naito, Masahiro Okamura
  • Patent number: 4415385
    Abstract: A dual-enclosure semi-closed diffusion wherein an outer enclosure is evacuatable and an inner enclosure has a limited aperture, the inner enclosure includes a diffusion vessel having an aperture and a baffle for partially blocking the aperture to leave the limited aperture.The outer enclosure is not directly exposed to impurity vapor and sustains a pressure difference, while the inner enclosure is not subjected to a substantial pressure difference.
    Type: Grant
    Filed: August 7, 1981
    Date of Patent: November 15, 1983
    Assignee: Hitachi, Ltd.
    Inventors: Osamu Saito, Hideo Homma, Hirokazu Inoue, Naohiro Momma
  • Patent number: 4402001
    Abstract: A semiconductor element such as a thyristor or a transistor which is capable of withstanding a high voltage comprises a semiconductor substrate of a pnpn-four layer structure (for a thyristor) or of a npn-three layer structure (for a transistor). An intermediate p-type layer is composed of a low concentration layer region located adjacent to an n-type layer and a high concentration layer region located adjacent to the other n-type layer. The high concentration layer region is formed through diffusion of aluminium so that the maximum concentration thereof becomes at least equal to 5.times.10.sup.16 atoms/cm.sup.3. A method of manufacturing such semiconductor element is also disclosed.
    Type: Grant
    Filed: January 12, 1978
    Date of Patent: August 30, 1983
    Assignee: Hitachi, Ltd.
    Inventors: Naohiro Momma, Hiroyuki Taniguchi
  • Patent number: 4266990
    Abstract: A process for the diffusion of aluminum into a semiconductor is disclosed. A piece of elemental aluminum used as a diffusion source is placed on a boat of a refractory metal and heated together with a semiconductor substrate in an evacuated sealed tube for diffusing aluminum into the semiconductor substrate. The semiconductor substrate having aluminum diffused therein is then subjected to heat treatment in an atmosphere of oxygen or nitrogen for a required length of time at a temperature higher than that used for the thermal diffusion. The above process provides the desired diffusion profile of aluminum, and a long lifetime of minority carriers in the substrate.
    Type: Grant
    Filed: October 25, 1979
    Date of Patent: May 12, 1981
    Assignee: Hitachi, Ltd.
    Inventors: Naohiro Momma, Hiroyuki Taniguchi