Abstract: A motor 1 according to an embodiment of the present disclosure includes a rotor 10 configured to freely rotate around a rotation axis AX; and a stator 20 arranged inside the rotor 10 and including a stator unit 21 of a claw-pole type, the stator unit including a winding wire 212 that is annularly wound around the rotation axis AX and a stator core 211 provided so as to surround the winding wire, wherein the stator 20 includes an inner space 24A around the rotation axis AX and in communication with an outer side of the rotor 10, such that heat can be radiated to the inner space 24A.

Abstract: The center console structure for a vehicle includes a console body; an armrest; and a power supply section that wirelessly transmits electric power to the mobile terminal via a placement surface on which the mobile terminal is placed. The console body includes a top plate section serving as an upper surface; a terminal accommodation section having the placement surface and arranged on a vehicle rear side of the top plate section and on a vehicle lower side of the armrest; and a right and left pair of console side surface sections arranged to oppose each other in a vehicle width direction with the terminal accommodation section being interposed therebetween.

Abstract: A semiconductor device that is resin-sealed in a wafer level after a rewiring layer forming process and a metal post forming process forming a metal post are performed on a semiconductor substrate of the semiconductor device includes devices formed on the semiconductor substrate. Further all of the devices are disposed in respective positions other than positions overlapping a peripheral border of the metal post when viewed from a top of the semiconductor substrate.

Abstract: A semiconductor device includes a semiconductor chip in which an internal circuit is formed, with the internal circuit having an output signal that fluctuates due to variation of fluctuation in electrical characteristics of multiple circuit elements constituting the internal circuit; a chip tab on which the semiconductor chip is mounted, with the semiconductor chip completely overlapping the chip tab and the circuit elements in the semiconductor chip arranged on the chip tab, and encapsulation resin within which the semiconductor chip and the chip tab are sealed. A horizontal surface area of the chip tab is smaller than that of the semiconductor chip, and a distance between a periphery of the chip tab and a periphery of the semiconductor chip is sufficient to cause stress exerted on the semiconductor chip by the encapsulation resin to be uniform across the horizontal surface area of the chip tab.

Abstract: A semiconductor device includes a semiconductor chip in which an internal circuit is formed, with the internal circuit having an output signal that fluctuates due to variation of fluctuation in electrical characteristics of multiple circuit elements constituting the internal circuit; a chip tab on which the semiconductor chip is mounted, with the semiconductor chip completely overlapping the chip tab and the circuit elements in the semiconductor chip arranged on the chip tab, and encapsulation resin within which the semiconductor chip and the chip tab are sealed. A horizontal surface area of the chip tab is smaller than that of the semiconductor chip, and a distance between a periphery of the chip tab and a periphery of the semiconductor chip is sufficient to cause stress exerted on the semiconductor chip by the encapsulation resin to be uniform across the horizontal surface area of the chip tab.

Abstract: A semiconductor device that is resin-sealed in a wafer level after a rewiring layer forming process and a metal post forming process forming a metal post are performed on a semiconductor substrate of the semiconductor device includes devices formed on the semiconductor substrate. Further all of the devices are disposed in respective positions other than positions overlapping a peripheral border of the metal post when viewed from a top of the semiconductor substrate.

Abstract: A semiconductor device has a configuration in which more than three kinds of wells are formed with small level differences. One kind of well from among the more than three kinds of wells has a surface level higher than other kinds of wells from among the more than three kinds of wells. The one kind of well is formed adjacent to and self-aligned to at least one kind of well from among the other kinds of wells. The other kinds of wells are different in one of a conductivity type, an impurity concentration and a junction depth, and include at least two kinds of wells having the same surface level.

Abstract: Disclosed is a net list generation method of generating a net list based on layout data; stress map data indicating stress distribution on a silicon chip, the stress being generated due to packaging of the silicon chip; and standard curve data indicating a relationship between the stress and characteristic variation of a device. The method includes the steps of reading data items from the layout data; reading a value of stress at the position of the device from the stress map data; reading the characteristic variation of the device, the characteristic variation corresponding to the value of the stress, from the standard curve data corresponding to the device; and correcting characteristics of the device based on the characteristic variation.

Abstract: A stress-distribution detecting semiconductor package group includes multiple stress-distribution detecting semiconductor packages each formed by resin-encapsulating a stress detecting semiconductor chip of the same size using an identical resin encapsulation structure. Each stress detecting semiconductor chip includes a piezoelectric element for stress detection and at least two electrode pads electrically connected to the piezoelectric element to measure an electrical property of the piezoelectric element. The piezoelectric elements of the stress detecting semiconductor chips are respectively disposed on the corresponding stress detecting semiconductor chips to be located at different positions from one another.

Abstract: A disclosed semiconductor device includes a MOS transistor that causes no problems concerning the formation of a thick gate insulating film and that is applicable to high withstand voltage devices. A drain region has a double diffusion structure including an N-drain region 3d and an N+ drain region 11d. A gate electrode includes a first gate electrode 9 formed on an insulating film 7 and a second gate electrode 13 formed on the first gate electrode 9 via a gate electrode insulating film 11. Between the gate insulating film 7 and the N+ source region 11s, a field insulating film 15 is disposed, over which an edge of the first gate electrode 9 is disposed. A gate voltage applied to the second gate electrode 13 via a gate wiring 13g is divided between the gate insulating film 7 and the gate electrode insulating film 11.

Abstract: A semiconductor device includes a semiconductor substrate and a metal-oxide semiconductor transistor. A first dielectric layer of the metal oxide semiconductor transistor overlaps source and drain electrodes and a channel region of the transistor. A first drain region is away from the channel region and the first dielectric layer. A second drain region is between the first drain region and the channel region. A gate electrode is on the first dielectric layer and connected to a gate wire, and includes first and second gate layers and a dielectric layer therebetween. The first gate layer has one edge laterally spaced from the first drain region and resting over the second drain region, and is isolated from the gate wire. The second gate layer is over the first gate layer and is connected to the gate wire.

Abstract: A semiconductor device is disclosed that comprises a high breakdown voltage MOSFET. The MOSFET includes a source region of a second conductivity type and a drain region of the second conductivity type formed apart from each other in a well region of a first conductivity type, a channel region formed between the source region and the drain region, a gate insulation film formed on the channel region, a LOCOS oxide film having greater film thickness than the gate insulation film, and a gate electrode formed across the gate insulation film and the LOCOS oxide film.

Abstract: A disclosed stress-distribution detecting semiconductor package group includes multiple stress-distribution detecting semiconductor packages each formed by resin-encapsulating a stress detecting semiconductor chip of the same size using an identical resin encapsulation structure. Each stress detecting semiconductor chip includes a piezoelectric element for stress detection and at least two electrode pads electrically connected to the piezoelectric element to measure an electrical property of the piezoelectric element. The piezoelectric elements of the stress detecting semiconductor chips are respectively disposed on the corresponding stress detecting semiconductor chips to be located at different positions from one another when superimposed on a single imaginary semiconductor chip plane having the same plane size as that of the stress detecting semiconductor chips.

Abstract: A semiconductor apparatus includes a device, two metal-wiring layers, and an insulation film. The device includes first and second electrodes. The two metal-wiring layers include uppermost and next-uppermost metal-wiring layers. The insulation film is formed on the uppermost metal-wiring layer and includes first and second pad openings. The uppermost metal-wiring layer has a first portion exposed to air through the first pad opening and forming a first electrode pad, and the uppermost metal-wiring layer has a second portion exposed to air through the second pad opening and forming a second electrode pad. The first and second electrode pads are located over the device and are electrically connected to the first and second electrodes, respectively. The next-uppermost metal-wiring layer has a first portion located under the first electrode pad and electrically connected thereto, and a second portion located under the second electrode pad and electrically connected thereto.

Abstract: A disclosed stress-distribution detecting semiconductor package group includes multiple stress-distribution detecting semiconductor packages each formed by resin-encapsulating a stress detecting semiconductor chip of the same size using an identical resin encapsulation structure. Each stress detecting semiconductor chip includes a piezoelectric element for stress detection and at least two electrode pads electrically connected to the piezoelectric element to measure an electrical property of the piezoelectric element. The piezoelectric elements of the stress detecting semiconductor chips are respectively disposed on the corresponding stress detecting semiconductor chips to be located at different positions from one another when superimposed on a single imaginary semiconductor chip plane having the same plane size as that of the stress detecting semiconductor chips.

Abstract: A disclosed semiconductor device includes a MOS transistor that causes no problems concerning the formation of a thick gate insulating film and that is applicable to high withstand voltage devices. A drain region has a double diffusion structure including an N-drain region 3d and an N+ drain region 11d. A gate electrode includes a first gate electrode 9 formed on an insulating film 7 and a second gate electrode 13 formed on the first gate electrode 9 via a gate electrode insulating film 11. Between the gate insulating film 7 and the N+ source region 11s, a field insulating film 15 is disposed, over which an edge of the first gate electrode 9 is disposed. A gate voltage applied to the second gate electrode 13 via a gate wiring 13g is divided between the gate insulating film 7 and the gate electrode insulating film 11.

Abstract: A disclosed stress-distribution detecting semiconductor package group includes multiple stress-distribution detecting semiconductor packages each formed by resin-encapsulating a stress detecting semiconductor chip of the same size using an identical resin encapsulation structure. Each stress detecting semiconductor chip includes a piezoelectric element for stress detection and at least two electrode pads electrically connected to the piezoelectric element to measure an electrical property of the piezoelectric element. The piezoelectric elements of the stress detecting semiconductor chips are respectively disposed on the corresponding stress detecting semiconductor chips to be located at different positions from one another when superimposed on a single imaginary semiconductor chip plane having the same plane size as that of the stress detecting semiconductor chips.

Abstract: A semiconductor device is disclosed that comprises a high breakdown voltage MOSFET. The MOSFET includes a source region of a second conductivity type and a drain region of the second conductivity type formed apart from each other in a well region of a first conductivity type, a channel region formed between the source region and the drain region, a gate insulation film formed on the channel region, a LOCOS oxide film having a greater film thickness than the gate insulation film and formed adjacent to the gate insulation film, and a gate electrode formed across the gate insulation film and the LOCOS oxide film.

Abstract: A disclosed semiconductor device includes a driver transistor including a source and a drain of a second conductive type provided with an interval therebetween in a semiconductor substrate of a first conductive type, a gate electrode extending in a predetermined direction and provided on the semiconductor substrate via a gate insulating film between the source and the drain, plural insular back gate diffusion layers of the first conductive type provided in the source so as to be in contact with the semiconductor substrate, wherein the back gate diffusion layers are spaced apart and arranged in the predetermined direction in the source, and a contact hole extending in the predetermined direction on the source and at least one of the back gate diffusion layers.

Abstract: A semiconductor device is disclosed that comprises a high breakdown voltage MOSFET. The MOSFET includes a source region of a second conductivity type and a drain region of the second conductivity type formed apart from each other in a well region of a first conductivity type, a channel region formed between the source region and the drain region, a gate insulation film formed on the channel region, a LOCOS oxide film having a greater film thickness than the gate insulation film and formed adjacent to the gate insulation film, and a gate electrode formed across the gate insulation film and the LOCOS oxide film.