Abstract: A voltage measurement device measures the voltage of at least one of series-connected battery cells, and includes one or more voltage detection circuits. Each voltage detection circuit includes: a first communication path; a mode control circuit that switches a mode of operation of the voltage detection circuit between normal and low-power modes; a first communication control circuit (communication control circuit) that transmits and receives a command signal to and from the first communication path; an activation signal detection circuit that detects an activation signal input from the first communication path; and an alarm generation circuit that, in the low-power mode, generates and outputs an alarm signal indicating an anomaly in the battery cells to the first communication path. In the low-power mode, when the activation signal detection circuit detects the activation signal, the mode control circuit switches the mode of operation to the normal mode.

Abstract: A voltage measurement device includes a first measurement circuit that measures voltage between both ends of a busbar, a second measurement circuit that measures voltage between both ends of each of a plurality of first battery cells and a plurality of second battery cells, and a correction circuit that corrects a measurement value measured by the second measurement circuit. The second measurement circuit is connected to the plurality of first battery cells, the busbar, and the plurality of second battery cells via the plurality of second RC filters. The correction circuit corrects a measurement value measured by the second measurement circuit using a measurement value of voltage between both ends of the busbar measured by the first measurement circuit.

Abstract: A voltage measurement system includes: a first reference signal transmission device (communication device) including a first master oscillator that generates a first master clock signal and a first reference signal generation circuit that generates a first reference signal based on the first master clock signal; and a first voltage measurement device including a first slave oscillator, a first correction circuit that corrects an oscillation frequency of the first slave oscillator based on the first reference signal, and a first voltage measurement circuit. The voltage measurement system includes: a normal mode; and a correction mode in which the first reference signal is transmitted from the first reference signal transmission device (communication device) to the first voltage measurement device, and the oscillation frequency of the first slave oscillator is synchronized with an oscillation frequency of the first master oscillator using the first reference signal.

Abstract: A cell stack management system includes a cell monitoring unit that measures an output voltage of a plurality of power storage cells, a battery management unit that manages a cell stack, and a first communication network that connects the cell monitoring unit and the battery management unit. The battery management unit includes: a first communication circuit connected to the first communication network; a second communication circuit connected to a second communication network for connecting to a higher-level system; a control circuit that controls the battery management unit; and a control circuit power supply. The cell stack management system includes a normal mode and a low-power mode as modes of operation. During transition from the low-power mode to the normal mode, the first communication circuit activates at least one of the control circuit power supply, the control circuit, or the second communication circuit.

Abstract: A voltage measurement device includes: a plurality of voltage detection circuits which measure cell voltages of a plurality of cells connected in series. Each of the plurality of voltage detection circuits includes: a device address generating circuit which generates a device address according to a first address assignment command received from a preceding voltage detection circuit located at a preceding stage; and an address assignment command generating circuit which generates a second address assignment command according to the first address assignment command, and sends the second address assignment command to a next voltage detection circuit located at a next stage.

Abstract: A voltage measurement device is a voltage measurement device including a plurality of voltage detection circuits which measure cell voltages of a plurality of cells connected in series. Each of the plurality of voltage detection circuits includes: a communication end information holding circuit which holds communication end information specifying, as at least one communication end position, at least one of the plurality of voltage detection circuits; and a communication control circuit which controls transfer for sending a communication command received from a preceding voltage detection circuit located at a preceding stage to a next voltage detection circuit located at a next stage, according to the communication end information.

Abstract: A voltage detection circuit is provided for measuring each cell voltage of an assembled battery configured by connecting a plurality of cells in series. The voltage detection circuit is defined as a first voltage detection circuit. The voltage detection circuit includes a downstream communication circuit that communicates with a host apparatus to communicate with a plurality of voltage detection circuits connected in series with each other; a reply signal generation circuit that generates a reply signal containing data detected by the first voltage detection circuit; an upstream transfer circuit that transfers a signal received by the upstream communication circuit to downstream; a dummy current consumption circuit that consumes a predetermined dummy current; and a control circuit that controls the reply signal generation circuit, the upstream transfer circuit, and the dummy current consumption circuit to selectively operate any one of them.

Abstract: A voltage detection circuit measures a plurality of cell voltages of an assembled battery configured by connecting a plurality of cells in series. The voltage detection circuit includes a plurality of input terminals connected to respective electrodes of the plurality of cells through a plurality of voltage detection lines; a multiplexer that periodically selects and outputs voltages of a plurality of cells in a group, a plurality of series cells configured as the group; an analog-to-digital (AD) converter that AD-converts an output voltage from the multiplexer and outputs digital data of the output voltage; and a control circuit that controls a timing for the selection by the multiplexer and a timing for the AD conversion. The control circuit switches over a time interval for which the multiplexer selects each of the cells to change a period of the AD conversion.

Abstract: A voltage detection circuit is provided for measuring each cell voltage of an assembled battery configured by connecting a plurality of cells in series. The voltage detection circuit is defined as a first voltage detection circuit. The voltage detection circuit includes a downstream communication circuit that communicates with a host apparatus to communicate with a plurality of voltage detection circuits connected in series with each other; a reply signal generation circuit that generates a reply signal containing data detected by the first voltage detection circuit; an upstream transfer circuit that transfers a signal received by the upstream communication circuit to downstream; a dummy current consumption circuit that consumes a predetermined dummy current; and a control circuit that controls the reply signal generation circuit, the upstream transfer circuit, and the dummy current consumption circuit to selectively operate any one of them.

Abstract: A voltage detection circuit measures a plurality of cell voltages of an assembled battery configured by connecting a plurality of cells in series. The voltage detection circuit includes a plurality of input terminals connected to respective electrodes of the plurality of cells through a plurality of voltage detection lines; a multiplexer that periodically selects and outputs voltages of a plurality of cells in a group, a plurality of series cells configured as the group; an analog-to-digital (AD) converter that AD-converts an output voltage from the multiplexer and outputs digital data of the output voltage; and a control circuit that controls a timing for the selection by the multiplexer and a timing for the AD conversion. The control circuit switches over a time interval for which the multiplexer selects each of the cells to change a period of the AD conversion.

Abstract: A voltage measurement device includes: a plurality of voltage detection circuits which measure cell voltages of a plurality of cells connected in series. Each of the plurality of voltage detection circuits includes: a device address generating circuit which generates a device address according to a first address assignment command received from a preceding voltage detection circuit located at a preceding stage; and an address assignment command generating circuit which generates a second address assignment command according to the first address assignment command, and sends the second address assignment command to a next voltage detection circuit located at a next stage.

Abstract: A voltage measurement device is a voltage measurement device including a plurality of voltage detection circuits which measure cell voltages of a plurality of cells connected in series. Each of the plurality of voltage detection circuits includes: a communication end information holding circuit which holds communication end information specifying, as at least one communication end position, at least one of the plurality of voltage detection circuits; and a communication control circuit which controls transfer for sending a communication command received from a preceding voltage detection circuit located at a preceding stage to a next voltage detection circuit located at a next stage, according to the communication end information.

Abstract: Each of n signal transition detection sections detects a transition of the signal level of at least one of a first input signal or a second input signal corresponding to the signal transition detection section. A time-division control section outputs a control pulse according to a system clock when a signal transition is detected by at least one of the n signal transition detection sections. Each of n output switching sections outputs either the first or the second input signal corresponding to the output switching section as a multiplexed signal according to the control pulse.

Abstract: A CCD charge transfer drive device includes: a timing signal generation unit that generates a first timing signal group including N timing signals representing CCD drive pulses; a control signal generation unit that generates a first control signal when a level change of any of the N timing signals is detected, the first control signal indicating a first enable period that is k times as long as one cycle of a system clock signal (k is an integer that is equal to or larger than N/2 and is closest to N/2); a time-division multiplexing unit that time-division multiplexes the N timing signals in the first enable period by time-division multiplexing two signals per cycle of the system clock signal; and a demultiplexing unit that demultiplexes the time-division multiplexed signal into the N timing signals.

Abstract: A variable delay circuit successively delays an input clock to generate a plurality of delayed clocks having different phases. A phase comparison circuit receives a first reference clock, which is either one of the delayed clocks or the input clock, and a second reference clock, which is one of the delayed clocks and whose phase lags behind that of the first reference clock, specifies a validated interval for the second reference clock, and compares the phases of the first and second reference clocks according to voltage levels of the first and second reference clocks only during the validated interval. A delay control circuit controls a delay time in the variable delay circuit according to a result of the comparison obtained by the phase comparison circuit.

Abstract: Each of n signal transition detection sections detects a transition of the signal level of at least one of a first input signal or a second input signal corresponding to the signal transition detection section. A time-division control section outputs a control pulse according to a system clock when a signal transition is detected by at least one of the n signal transition detection sections. Each of n output switching sections outputs either the first or the second input signal corresponding to the output switching section as a multiplexed signal according to the control pulse.

Abstract: A front-end signal processing circuit that stabilizes a black level of an output signal of an image sensor in a prescribed set level, without being influenced by a DC offset component of circuit elements making up a feedback loop, and an imaging device including such the front-end signal processing circuit, are provided. The front-end signal processing circuit includes a feedback loop made up of a luminance detecting/digitizing section and a black level clamp section, and clamps a black level of an output signal of an image sensor to a prescribed set level. The front-end signal processing circuit further includes an offset correction section. The offset correction section stores an offset value being a difference between a signal level of an OB region of the image sensor and the prescribed level, subtracts the offset value from a digital luminance signal corresponding to an effective pixel region of the image sensor, and outputs the obtained signal.

Abstract: A variable delay circuit successively delays an input clock to generate a plurality of delayed clocks having different phases. A phase comparison circuit receives a first reference clock, which is either one of the delayed clocks or the input clock, and a second reference clock, which is one of the delayed clocks and whose phase lags behind that of the first reference clock, specifies a validated interval for the second reference clock, and compares the phases of the first and second reference clocks according to voltage levels of the first and second reference clocks only during the validated interval. A delay control circuit controls a delay time in the variable delay circuit according to a result of the comparison obtained by the phase comparison circuit.

Abstract: (a) The luminance levels of the optical black part pixels included in the output signal of an image sensor are detected and digitized, (b) the digitized luminance levels of the optical black part pixels are averaged, (c) the number of pixels on which averaging is performed is counted, (d) a control signal is generated when the count value of the number of pixels reaches a predetermined value, (e) the black level of the output signal of the image sensor is determined from the averaged luminance level in response to the control signal, and (f) the luminance levels of the effective part pixels included in the output signal of the image sensor whose black level is determined are detected and digitized.

Abstract: A pipeline A/D converter of the present invention includes a plurality of stages each operating for A/D conversion and a digital computing portion that outputs an A/D converted signal based on a digital signal output from each of the stages. In each of the stages, an analog signal from the preceding stage is sampled by passive elements C1 and C2 in a first period, and one of the passive elements is used as a feedback element in a second period to perform adding/subtracting with respect to the signal sampled by the other passive element. By the control from the digital computing portion, a test signal Tink is used instead of an analog output signal Vo(k?1), and a unique conversion-error value is detected and corrected based on the digital signal obtained by the operation of each of the stages. It is possible to obtain a high-resolution A/D convert that can suppress a conversion error caused by the relative error of capacitors used for analog signal processing without decreasing the speed of A/D conversion.