Abstract: A front-end signal processing circuit that stabilizes a black level of an output signal of an image sensor in a prescribed set level, without being influenced by a DC offset component of circuit elements making up a feedback loop, and an imaging device including such the front-end signal processing circuit, are provided. The front-end signal processing circuit includes a feedback loop made up of a luminance detecting/digitizing section and a black level clamp section, and clamps a black level of an output signal of an image sensor to a prescribed set level. The front-end signal processing circuit further includes an offset correction section. The offset correction section stores an offset value being a difference between a signal level of an OB region of the image sensor and the prescribed level, subtracts the offset value from a digital luminance signal corresponding to an effective pixel region of the image sensor, and outputs the obtained signal.

Abstract: A pipeline A/D converter of the present invention includes a plurality of stages each operating for A/D conversion and a digital computing portion that outputs an A/D converted signal based on a digital signal output from each of the stages. In each of the stages, an analog signal from the preceding stage is sampled by passive elements C1 and C2 in a first period, and one of the passive elements is used as a feedback element in a second period to perform adding/subtracting with respect to the signal sampled by the other passive element. By the control from the digital computing portion, a test signal Tink is used instead of an analog output signal Vo(k?1), and a unique conversion-error value is detected and corrected based on the digital signal obtained by the operation of each of the stages. It is possible to obtain a high-resolution A/D convert that can suppress a conversion error caused by the relative error of capacitors used for analog signal processing without decreasing the speed of A/D conversion.

Abstract: A phase adjustment device which adjusts a phase difference between a first output pulse signal and a second output pulse signal according to a phase difference between a first input pulse signal and a second input pulse signal, the phase adjustment device including: a first selection unit which selects one of the first input pulse signal and an adjustment pulse signal that is used for adjustment; a second selection unit which selects one of the second input pulse signal and the adjustment pulse signal; a first delay unit which delays the signal selected by the second selection unit, and a delay amount of the first delay unit is adjustable; a first output unit which outputs, as the first output pulse signal, the signal selected by the first selection unit; a second output unit which outputs, as the second output pulse signal, the signal delayed by the first delay unit; and a phase adjustment unit which adjusts the delay amount so as to equalize phases of the first output pulse signal and the second output puls

Abstract: In a CCD solid-state image pick-up device according to the present invention, a solid-state image pick-up circuit formed by a sensor part, a horizontal transfer register part and a floating diffusion amplifier converts a photo signal into a voltage signal and outputs the voltage signal, and a voltage-current conversion circuit converts the voltage signal output from the solid-state image pick-up circuit into a current signal. A current-driven black signal component detect/remove circuit then removes a black signal component from the current signal output from the CCD solid-state image pick-up device, and an image signal component alone is output as a current image signal. A current-voltage conversion circuit converts the current image signal into a voltage image signal.

Abstract: In a gate array having adjacent lines of PFETs and NFETs along a first axis, some gates of PFETs and/or NFETs extend into the region between wells and along a first (x) axis of the lines of transistors to overlap along the axis, so that an extended gate of an nth transistor, a gate of an (n−1)th non-extended transistor and a gate of an (n−1)th non-extended transistor of the opposite polarity lie along an axis (y) perpendicular to the first axis. In a rectangular layout, the upper right transistor (having an extended gate) is connected to the lower left transistor by a short connection along the y axis.

Abstract: In a gate array having adjacent lines of PFETs and NFETs along a first axis, some gates of PFETs and/or NFETs extend into the region between wells and along a first (x) axis of the lines of transistors to overlap along the axis, so that an extended gate of an nth transistor, a gate of an (n-1)th non-extended transistor and a gate of an (n−1)th non-extended transistor of the opposite polarity lie along an axis (y) perpendicular to the first axis. In a rectangular layout, the upper right transistor (having an extended gate) is connected to the lower left transistor by a short connection along the y axis.

Abstract: To provide a D/A converter and a D/A converting method in which a nonlinear error of an analog output obtained in accordance with a digital input can be decreased without using any specific analog process. An n-bit D/A converter (2) includes: correction signal generating means (4) for generating an m-bit digital correction signal (wherein m is a positive integer) in accordance with an n-bit digital input signal D (wherein n is a positive integer of 2 or more); and D/A conversion means (6) for converting an (n+m)-bit digital signal consisting of the n-bit input signal D and the m-bit correction signal into an analog signal.

Abstract: A differential input interface circuit includes a reference level generation stage generating a DC level that coincides with the DC level within the system; capacitors for cutting-off the DC level of the differential input signals; resistors for matching the average of the non-inverting phase signal and the inverting phase signal of the differential input signals from which the DC levels have been cut-off on the output DC level generated by the reference level generation stage. Thus, a differential input interface circuit make it possible to match the DC level of differential inputs to the DC level within a system which is responsive to the differential inputs.

Abstract: An analog voltage comparator for suppressing an input voltage offset is described. The voltage comparator includes: a first and a second input comparator, both operating in opposite phases, and third comparator coupled to the two input comparators. The circuit further includes a first switch connected a first capacitor coupled to a negative input of the first comparator and to the positive input of the second comparator for alternatively supplying either an input voltage Vi or a reference voltage Vref to the negative and positive input, respectively. It further includes a second capacitor between the positive input of the first comparator and the negative input of the second comparator; a second switch between the negative input and an output of the first comparator; and a third switch between the negative input and an output of the second comparator.