Abstract: Disclosed herein is an apparatus that includes a first semiconductor chip having a plurality of pad electrodes and a plurality of first latch circuits assigned to an associated one of the pad electrodes, a second semiconductor chip having a plurality of TSVs each electrically connected to an associated one of the pad electrodes and a plurality of second latch circuits assigned to an associated one of the TSVs, and a training circuit configured to perform a training operation on a signal path including the selected one of the pad electrodes and the selected one of the TSVs. The training circuit is configured to activate a fail signal when the signal path is determined to be defective. The fail signal is stored in the selected one of the first latch circuits and the selected one of the second latch circuits.

Abstract: Disclosed is a plurality of through-silicon vias (TSVs) and related systems, methods, and devices. An electronic device includes a stack of chips, a first TSV, and a second TSV. The stack of chips includes one or more side edges at a perimeter of the stack of chips. A TSV zone of the stack of chips is within a predetermined distance from the one or more side edges. The first TSV is within the TSV zone of the stack of chips at a first distance from the one or more side edges. The second TSV is within the TSV zone of the stack of chips at a second distance from the one or more side edges. The second distance is shorter than the first distance.

Abstract: Disclosed herein is an apparatus that includes a memory cell array, a plurality of TSVs penetrating a semiconductor chip, an output circuit configured to output a data to the TSVs, an input circuit configured to receive a data from the TSVs, a pad supplied with a data from outside, and a control circuit configured to write the data to the memory cell array, read the data from the memory cell array, and transfer the data from the memory cell array to the input circuit via the output circuit and the TSVs.

Abstract: Disclosed herein is an apparatus that includes a first semiconductor chip having a plurality of pad electrodes and a plurality of first latch circuits assigned to an associated one of the pad electrodes, a second semiconductor chip having a plurality of TSVs each electrically connected to an associated one of the pad electrodes and a plurality of second latch circuits assigned to an associated one of the TSVs, and a training circuit configured to perform a training operation on a signal path including the selected one of the pad electrodes and the selected one of the TSVs. The training circuit is configured to activate a fail signal when the signal path is determined to be defective. The fail signal is stored in the selected one of the first latch circuits and the selected one of the second latch circuits.

Abstract: Disclosed herein is an apparatus that includes a memory cell array, a plurality of TSVs penetrating a semiconductor chip, an output circuit configured to output a data to the TSVs, an input circuit configured to receive a data from the TSVs, a pad supplied with a data from outside, and a control circuit configured to write the data to the memory cell array, read the data from the memory cell array, and transfer the data from the memory cell array to the input circuit via the output circuit and the TSVs.

Abstract: Examples described herein include apparatuses and methods TSV resistance and short measurement in a stacked device. An example apparatus may include a chip comprising semiconductor substrate including a first surface and a second surface opposite to the first surface. The chip may include a first terminal formed above the first surface, a second terminal formed above the second surface, a buffer circuit coupled between the first and second terminals, a first through-substrate via (TSV) penetrating the semiconductor substrate, and a first switch coupled between the first terminal and the first TSV.

Abstract: Disclosed is a plurality of through-silicon vias (TSVs) and related systems, methods, and devices. An electronic device includes a stack of chips, a first TSV, and a second TSV. The stack of chips includes one or more side edges at a perimeter of the stack of chips. A TSV zone of the stack of chips is within a predetermined distance from the one or more side edges. The first TSV is within the TSV zone of the stack of chips at a first distance from the one or more side edges. The second TSV is within the TSV zone of the stack of chips at a second distance from the one or more side edges. The second distance is shorter than the first distance.

Abstract: Disclosed herein is an apparatus that includes a first semiconductor chip having a plurality of pad electrodes and a plurality of first latch circuits assigned to an associated one of the pad electrodes, a second semiconductor chip having a plurality of TSVs each electrically connected to an associated one of the pad electrodes and a plurality of second latch circuits assigned to an associated one of the TSVs, and a training circuit configured to perform a training operation on a signal path including the selected one of the pad electrodes and the selected one of the TSVs. The training circuit is configured to activate a fail signal when the signal path is determined to be defective. The fail signal is stored in the selected one of the first latch circuits and the selected one of the second latch circuits.

Abstract: Disclosed herein is an apparatus that includes a memory cell army, a plurality of TSVs penetrating a semiconductor chip, an output circuit configured to output a data to the TSVs, an input circuit configured to receive a data from the TSVs, a pad supplied with a data from outside, and a control circuit configured to write the data to the memory cell array, read the data from the memory cell array, and transfer the data from the memory cell array to the input circuit via the output circuit and the TSVs.

Abstract: Examples described herein include apparatuses and methods TSV resistance and short measurement in a stacked device. An example apparatus may include a chip comprising semiconductor substrate including a first surface and a second surface opposite to the first surface. The chip may include a first terminal formed above the first surface, a second terminal formed above the second surface, a buffer circuit coupled between the first and second terminals, a first through-substrate via (TSV) penetrating the semiconductor substrate, and a first switch coupled between the first terminal and the first TSV.

Abstract: Examples described herein include apparatuses and methods TSV resistance and short measurement in a stacked device. An example apparatus may include a chip comprising semiconductor substrate including a first surface and a second surface opposite to the first surface. The chip may include a first terminal formed above the first surface, a second terminal formed above the second surface, a buffer circuit coupled between the first and second terminals, a first through-substrate via (TSV) penetrating the semiconductor substrate, and a first switch coupled between the first terminal and the first TSV.

Abstract: Examples described herein include apparatuses and methods TSV resistance and short measurement in a stacked device. An example apparatus may include a chip comprising semiconductor substrate including a first surface and a second surface opposite to the first surface. The chip may include a first terminal formed above the first surface, a second terminal formed above the second surface, a buffer circuit coupled between the first and second terminals, a first through-substrate via (TSV) penetrating the semiconductor substrate, and a first switch coupled between the first terminal and the first TSV.

Abstract: A method includes resetting an output timing adjustment circuit in each of a plurality of DRAM devices to a default output timing data value, measuring a default delay from read command to read data for each of the plurality of DRAM devices, identifying a slowest DRAM device having a maximum default delay from read command to read data among the plurality of DRAM devices, writing an output timing data value to the output timing adjustment circuit in each of the plurality of DRAM devices to set the delay from read command to read data for each respective DRAM device to an amount substantially equal to the maximum default delay, and reading data from any one of the plurality of DRAM devices with a delay from read command to read data substantially equal to the maximum default delay.

Abstract: A method includes resetting an output timing adjustment circuit in each of a plurality of DRAM devices to a default output timing data value, measuring a default delay from read command to read data for each of the plurality of DRAM devices, identifying a slowest DRAM device having a maximum default delay from read command to read data among the plurality of DRAM devices, writing an output timing data value to the output timing adjustment circuit in each of the plurality of DRAM devices to set the delay from read command to read data for each respective DRAM device to an amount substantially equal to the maximum default delay, and reading data from any one of the plurality of DRAM devices with a delay from read command to read data substantially equal to the maximum default delay.

Abstract: A method includes resetting an output timing adjustment circuit in each of a plurality of DRAM devices to a default output timing data value, measuring a default delay from read command to read data for each of the plurality of DRAM devices, identifying a slowest DRAM device having a maximum default delay from read command to read data among the plurality of DRAM devices, writing an output timing data value to the output timing adjustment circuit in each of the plurality of DRAM devices to set the delay from read command to read data for each respective DRAM device to an amount substantially equal to the maximum default delay, and reading data from any one of the plurality of DRAM devices with a delay from read command to read data substantially equal to the maximum default delay.

Abstract: A semiconductor chip includes a memory array including a plurality of memory cells, a plurality of terminals including a plurality of test terminals to output a result of a specific test, and a circuit that outputs the result to a selected one of the plurality of test terminals based on a chip identification data.

Abstract: A semiconductor device has an antifuse element and a measurement unit. The antifuse element stores information according to whether the antifuse element is in the broken or unbroken state. The measurement unit determines a resistance value related to the resistance value of the broken antifuse element.

Abstract: A method includes resetting an output timing adjustment circuit in each of a plurality of DRAM devices to a default output timing data value, measuring a default delay from read command to read data for each of the plurality of DRAM devices, identifying a slowest DRAM device having a maximum default delay from read command to read data among the plurality of DRAM devices, writing an output timing data value to the output timing adjustment circuit in each of the plurality of DRAM devices to set the delay from read command to read data for each respective DRAM device to an amount substantially equal to the maximum default delay, and reading data from any one of the plurality of DRAM devices with a delay from read command to read data substantially equal to the maximum default delay.

Abstract: A semiconductor device includes an interface chip including: an internal data terminal, and a timing data storage circuit configured to output a plurality of timing set signals, and a plurality of core chips stacked with one another, each of the core chips including a plurality of memory cells, an output control circuit coupled to the timing data storage circuit of the interface chip, the output control circuit being configured to receive a corresponding one of the timing set signals and to output an output timing signal in response to the corresponding one of the timing set signals, and a data output circuit coupled to the internal data terminal of the interface chip, the data output circuit being configured to output data in response to the output timing signal, the data being derived from a corresponding one of the memory cells.

Abstract: A method includes resetting an output timing adjustment circuit in each of a plurality of DRAM devices to a default output timing data value, measuring a default delay from read command to read data for each of the plurality of DRAM devices, identifying a slowest DRAM device having a maximum default delay from read command to read data among the plurality of DRAM devices, writing an output timing data value to the output timing adjustment circuit in each of the plurality of DRAM devices to set the delay from read command to read data for each respective DRAM device to an amount substantially equal to the maximum default delay, and reading data from any one of the plurality of DRAM devices with a delay from read command to read data substantially equal to the maximum default delay.