Abstract: Read data that are output from core chips are accurately captured into an interface chip. Each of the core chips includes a data output circuit that outputs read data to the interface chip in response to a read command, and an output timing adjustment circuit that adjusts the period of time required from the reception of the read command to the outputting of the read data from the data output circuit. The interface chip includes a data input circuit that captures read data, and an input timing adjustment circuit that adjusts the timing for the data input circuit to allow the capturing of the read data after issuing the read command. In this manner, a sufficient latch margin for read data on the interface chip side can be secured.

Abstract: A device includes a first semiconductor chip that includes a first memory cell array including a plurality of first memory cells, a first control logic circuit accessing the first memory cell array and producing a plurality of first data signals in response to data stored in selected ones of the first memory cells, a plurality of first data electrodes, and a first data control circuit coupled to the first control logic circuit and the first data electrodes. A second semiconductor chip includes a second memory cell array including a plurality of second memory cells, a second control logic circuit accessing the second memory cell array and producing a plurality of second data signals in response to data stored in selected ones of the second memory cells. The second control logic circuit is configured to store second timing adjustment information and to produce a second output timing signal.

Abstract: plurality of core chips to which chip identification information different from each other is allocated and an interface chip are layered, the plurality of core chips are commonly connected to the interface chip through a first current path including at least a through silicon via, the interface chip serially supplies an enable signal to the plurality of core chips through the first current path, and the plurality of core chips are activated based on a logic level of a bit corresponding to the chip identification information among a plurality of bits configuring the enable signal. The present invention can reduce the number of through silicon vias required to supply an enable signal.

Abstract: Each of the core chips includes a data output circuit that outputs read data to the interface chip in response to a read command, and an output timing adjustment circuit that equalizes the periods of time required between the reception of the read command and the outputting of the read data from the data output circuit among the core chips. With this arrangement, a sufficient latch margin for read data to be input can be secured on the interface chip side. Furthermore, as the output timing is adjusted on each core chip side, there is no need to prepare the same number of latch timing control circuits as the number of core chips on the interface chip side.

Abstract: The semiconductor memory device includes plural core chips that are allocated with different chip identification information from each other and an interface chip that controls the plural core chips. A bit number of external unit data that is simultaneously input and output between an external device and the interface chip changes in the interface chip, and the interface chip changes chip selection information for comparison with the chip identification information, according to the bit number of the external unit data. As a result, the page configuration does not need to be changed, when the I/O configuration is changed.

Abstract: A semiconductor device includes a plurality of memory chips arranged in a layered manner, each including a substrate and a memory cell array, and a plurality of current paths provided while penetrating through the memory chips. Each of the memory chips includes a test circuit that reads test data from a corresponding one of the memory cell array and outputs a layer test result signal responding to the test data to a different current path for each of the memory chips.

Abstract: The core chips each include a timing control circuit that outputs a timing signal synchronized with the outputting of parallel data to the interface chip. The interface chip includes a data input circuit that captures parallel data in synchronization with the timing signal. With this arrangement, the timing to output the parallel data and the timing to capture the parallel data are both synchronized with the timing signal generated in the core chips. Therefore, even if there is a difference in operation speed between each core chip and the interface chip, the parallel data can be accurately captured on the interface chip side.

Abstract: Read data that are output from core chips are accurately captured into an interface chip. Each of the core chips includes a data output circuit that outputs read data to the interface chip in response to a read command, and an output timing adjustment circuit that adjusts the period of time required from the reception of the read command to the outputting of the read data from the data output circuit. The interface chip includes a data input circuit that captures read data, and an input timing adjustment circuit that adjusts the timing for the data input circuit to allow the capturing of the read data after issuing the read command. In this manner, a sufficient latch margin for read data on the interface chip side can be secured.

Abstract: A semiconductor memory device includes plural banks, defect relief circuits individually provided for these banks, a defective-address storing circuit that stores defective addresses, and a comparing circuit that compares an access-requested address with a defective address. The defective-address storing circuit and the comparing circuit are allocated in common to two banks, respectively. With this arrangement, a chip area can be decreased.

Abstract: A semiconductor device has an antifuse element and a measurement unit. The antifuse element stores information according to whether the antifuse element is in the broken or unbroken state. The measurement unit determines a resistance value related to the resistance value of the broken antifuse element.

Abstract: A fuse circuit uses an electrically writable fuse circuit and comprises a first fuse unit provided with a first electrically writable fuse, and a second fuse unit provided with a second electrically writable fuse, and the state of logical add of the states of the first and second fuse units is used as the output of the electrically writable fuse circuit in the first and second fuse units. Reliability in writing in of the fuse can be improved by using such a fuse circuit for a redundancy decoder circuit or the like.

Abstract: A DLL Reset signal for delivering Fuse data from anti-fuses is generated from a reset signal which is supplied asynchronous to a clock when an initial setting is made. The DLL Reset signal is supplied to an anti-fuse block which comprises a plurality of anti-fuses, such that the delay amount of an internal signal is switched to a desired value in accordance with the Fuse data written into the anti-fuses.

Abstract: A DLL Reset signal for delivering Fuse data from anti-fuses is generated from a reset signal which is supplied asynchronous to a clock when an initial setting is made. The DLL Reset signal is supplied to an anti-fuse block which comprises a plurality of anti-fuses, such that the delay amount of an internal signal is switched to a desired value in accordance with the Fuse data written into the anti-fuses.

Abstract: A fuse circuit according to the present invention uses an electrically writable fuse circuit and comprises a first fuse unit provided with a first electrically writable fuse, and a second fuse unit provided with a second electrically writable fuse, and the state of logical add of the states of the first and second fuse units is used as the output of the electrically writable fuse circuit in the first and second fuse units. Reliability in writing in of the fuse can be improved by using such a fuse circuit for a redundancy decoder circuit or the like.

Abstract: A semiconductor device having an internal voltage, signal timing, and logic current supply determined by a desired operating frequency is disclosed. The semiconductor device may include a register (1100) that may store a code value received externally during a code setting operation. A decoder (1200) may decode the code value and provide decoded signals (D1 to D4) to an internal power source circuit (1300), internal logic circuit system (1400), and a sense amp system (1500). The internal power source circuit (1300) may generate a power supply voltage based on the code value. The internal logic circuit system (1400) may be coupled to receive the power supply voltage and may generate a signal delay based on the code value. The sense amp system (1500) may be coupled to receive the power supply voltage and may have a operating current based on the code value. In this way, signal timings may be improved and power consumption may be reduced.

Abstract: In an array of memory cells, multiple prechargers are respectively connected to bit-line pairs of the array. Near-end balancers and far-end balancers are connected to opposite ends of the bit-line pairs. During a read mode of the memory, the prechargers and both near-end and far-end balancers are activated. For power savings purposes, during a write mode the prechargers and the far-end balancers remain inactive and the near-end balancers are activated.

Abstract: A semiconductor device having an internal voltage, signal timing, and logic current supply determined by a desired operating frequency is disclosed. The semiconductor device may include a register (1100) that may store a code value received externally during a code setting operation. A decoder (1200) may decode the code value and provide decoded signals (D1 to D4) to an internal power source circuit (1300), internal logic circuit system (1400), and a sense amp system (1500). The internal power source circuit (1300) may generate a power supply voltage based on the code value. The internal logic circuit system (1400) may be coupled to receive the power supply voltage and may generate a signal delay based on the code value. The sense amp system (1500) may be coupled to receive the power supply voltage and may have a operating current based on the code value. In this way, signal timings may be improved and power consumption may be reduced.

Abstract: In an array of memory cells, multiple prechargers are respectively connected to bit-line pairs of the array. Near-end balancers and far-end balancers are connected to opposite ends of the bit-line pairs. During a read mode of the memory, the prechargers and both near-end and far-end balancers are activated. For power savings purposes, during a write mode the prechargers and the far-end balancers remain inactive and the near-end balancers are activated.