Patents by Inventor Naoki Izumi

Naoki Izumi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9406794
    Abstract: A semiconductor device according to the present invention includes a semiconductor layer. A first conductivity type region is formed on a base layer portion of the semiconductor layer. A body region of a second conductivity type is formed on the semiconductor layer to be in contact with the first conductivity type region. A trench in which a gate electrode is embedded through a gate insulating film is formed on the semiconductor layer. The trench penetrates through the body region, so that a deepest portion thereof reaches the first conductivity type region. A source region of the first conductivity type is formed on a surface layer portion of the semiconductor layer around the trench. The gate insulating film includes a thick-film portion having a relatively large thickness on a bottom surface of the trench.
    Type: Grant
    Filed: February 13, 2012
    Date of Patent: August 2, 2016
    Assignee: ROHM CO., LTD.
    Inventor: Naoki Izumi
  • Publication number: 20160190311
    Abstract: A semiconductor device according to the present invention includes: an insulating layer; a semiconductor layer of a first conductive type laminated on the insulating layer; an annular deep trench having a thickness reaching the insulating layer from a top surface of the semiconductor layer; a body region of a second conductive type formed across an entire thickness of the semiconductor layer along a side surface of the deep trench in an element forming region surrounded by the deep trench; a drift region of the first conductive type constituted of a remainder region besides the body region in the element forming region; a source region of the first conductive type formed in a top layer portion of the body region; a drain region of the first conductive type formed in a top layer portion of the drift region; and a first conductive type region formed in the drift region, having a deepest portion reaching a position deeper than the drain region, and having a first conductive type impurity concentration higher tha
    Type: Application
    Filed: March 7, 2016
    Publication date: June 30, 2016
    Applicant: ROHM CO., LTD.
    Inventors: Naoki IZUMI, Tomoyasu SADA
  • Patent number: 9337256
    Abstract: A method of manufacturing a semiconductor device having a VDMOSFET (Vertical Double-diffused Metal Oxide Semiconductor Field-Effect Transistor) and a planar gate MOSFET (Metal Oxide Semiconductor Field-Effect Transistor), including forming a semiconductor layer of a first conductivity type by epitaxy, forming a body region recess for forming a body region of the VDMOSFET on the semiconductor layer, and embedding a semiconductor material of a second conductivity type in the body region recess by epitaxy or CVD (Chemical Vapor Deposition).
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: May 10, 2016
    Assignee: ROHM CO., LTD.
    Inventor: Naoki Izumi
  • Publication number: 20160097635
    Abstract: A positioning unit includes two or more the laser light sources disposed around a point sensor. Laser light beams from the two or more the laser light sources intersect at an adjustment point separated from a detection point, which is away from the point sensor, by a predetermined distance. The adjustment point is positioned on a desired measurement start point on a work, the point sensor is moved close to the work by the predetermined distance, and a measurement scan of the work is started.
    Type: Application
    Filed: September 30, 2015
    Publication date: April 7, 2016
    Inventors: Kotaro Hirano, Naoki Izumi, Hideki Shindo
  • Patent number: 9299833
    Abstract: A semiconductor device according to the present invention includes: an insulating layer; a semiconductor layer of a first conductive type laminated on the insulating layer; an annular deep trench having a thickness reaching the insulating layer from a top surface of the semiconductor layer; a body region of a second conductive type formed across an entire thickness of the semiconductor layer along a side surface of the deep trench in an element forming region surrounded by the deep trench; a drift region of the first conductive type constituted of a remainder region besides the body region in the element forming region; a source region of the first conductive type formed in a top layer portion of the body region; a drain region of the first conductive type formed in a top layer portion of the drift region; and a first conductive type region formed in the drift region, having a deepest portion reaching a position deeper than the drain region, and having a first conductive type impurity concentration higher tha
    Type: Grant
    Filed: September 9, 2008
    Date of Patent: March 29, 2016
    Assignee: ROHM CO., LTD.
    Inventors: Naoki Izumi, Tomoyasu Sada
  • Publication number: 20150082926
    Abstract: A traction nut has twist rollers pivotally supported so as to be rotatable in a state of defining an inclination angle with respect to an axis of a drive shaft, the inclination angle being equivalent to a lead angle; an open/close lever provided to switch between a friction-contact state and a disengaged state of the traction nut relative to the drive shaft; and a spring generating a biasing force such that the traction nut is brought into friction-contact with the drive shaft. In response to user operation, the open/close lever puts the traction nut in the disengaged state against the biasing force of the spring. When the user releases the open/close lever, the traction nut returns to the friction-contact state due to the biasing force of the spring.
    Type: Application
    Filed: September 16, 2014
    Publication date: March 26, 2015
    Inventors: Youhei ONODERA, Hideki SHINDO, Naoki IZUMI
  • Patent number: 8975686
    Abstract: A semiconductor device includes a semiconductor layer with a trench dug downward from its surface, a source region formed on a surface layer portion adjacent to a first side of the trench in a prescribed direction, a drain region formed on the surface layer portion, adjacent to a second side of the trench opposite to the first side in the prescribed direction, a first insulating film on the bottom surface and the side surface of the trench, a floating gate stacked on the first insulating film and opposed to the bottom surface and the side surface of the trench through the first insulating film, a second insulating film formed on the floating gate, and a control gate at least partially embedded in the trench so that the portion embedded in the trench is opposed to the floating gate through the second insulating film.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: March 10, 2015
    Assignee: Rohm Co., Ltd.
    Inventor: Naoki Izumi
  • Patent number: 8829679
    Abstract: A semiconductor device wherein destruction of a sealing ring caused by cracking of an interlayer dielectric film is difficult to occur, as well as a method for manufacturing the semiconductor device, are provided. A first laminate comprises first interlayer dielectric films having a first mechanical strength. A second laminate comprises second interlayer dielectric films having a mechanical strength higher than the first mechanical strength. A first region includes first metallic layers and vias provided within the first laminate. A second region includes second metallic layers and vias provided within the second laminate. When seen in plan, the second region overlaps at least a part of the first region, is not coupled with the first region by vias, and sandwiches the second interlayer dielectric film between it and the first region.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: September 9, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroyuki Chibahara, Atsushi Ishii, Naoki Izumi, Masahiro Matsumoto
  • Publication number: 20140183616
    Abstract: A semiconductor device includes a semiconductor layer with a trench dug downward from its surface, a source region formed on a surface layer portion adjacent to a first side of the trench in a prescribed direction, a drain region formed on the surface layer portion, adjacent to a second side of the trench opposite to the first side in the prescribed direction, a first insulating film on the bottom surface and the side surface of the trench, a floating gate stacked on the first insulating film and opposed to the bottom surface and the side surface of the trench through the first insulating film, a second insulating film formed on the floating gate, and a control gate at least partially embedded in the trench so that the portion embedded in the trench is opposed to the floating gate through the second insulating film.
    Type: Application
    Filed: March 7, 2014
    Publication date: July 3, 2014
    Applicant: ROHM CO., LTD.
    Inventor: Naoki IZUMI
  • Patent number: 8692308
    Abstract: A semiconductor device includes a semiconductor layer with a trench dug downward from its surface, a source region formed on a surface layer portion adjacent to a first side of the trench in a prescribed direction, a drain region formed on the surface layer portion, adjacent to a second side of the trench opposite to the first side in the prescribed direction, a first insulating film on the bottom surface and the side surface of the trench, a floating gate stacked on the first insulating film and opposed to the bottom surface and the side surface of the trench through the first insulating film, a second insulating film formed on the floating gate, and a control gate at least partially embedded in the trench so that the portion embedded in the trench is opposed to the floating gate through the second insulating film.
    Type: Grant
    Filed: June 18, 2012
    Date of Patent: April 8, 2014
    Assignee: Rohm Co., Ltd.
    Inventor: Naoki Izumi
  • Patent number: 8652880
    Abstract: To provide a technique that can improve the data retention characteristic of an MRAM device by improving the resistance against an external magnetic field in a semiconductor device including the MRAM device. A first magnetic shield material is disposed over a die pad via a first die attach film. Then, a semiconductor chip is mounted over the first magnetic shield material via a second die attach film. Furthermore, a second magnetic shield material is disposed over the semiconductor chip via a third die attach film. That is, the semiconductor chip is disposed so as to be sandwiched by the first magnetic shield material and the second magnetic shield material. At this time, while the planar area of the second magnetic shield material is smaller than that of the first magnetic shield material, the thickness of the second magnetic shield material is thicker than that of the first magnetic shield material.
    Type: Grant
    Filed: August 10, 2012
    Date of Patent: February 18, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Koji Bando, Kazuyuki Misumi, Tatsuhiko Akiyama, Naoki Izumi, Akira Yamazaki
  • Publication number: 20130270633
    Abstract: A semiconductor device according to the present invention includes: a body region of a first conductive type; trenches formed by digging in from a top surface of the body region; gate electrodes embedded in the trenches; source regions of a second conductive type formed at sides of the trenches in a top layer portion of the body region; and body contact regions of the first conductive type, penetrating through the source regions in a thickness direction and contacting the body region. The body contact regions are formed in a zigzag alignment in a plan view.
    Type: Application
    Filed: June 10, 2013
    Publication date: October 17, 2013
    Inventor: Naoki IZUMI
  • Patent number: 8476702
    Abstract: A semiconductor device according to the present invention includes: a body region of a first conductive type; trenches formed by digging in from a top surface of the body region; gate electrodes embedded in the trenches; source regions of a second conductive type formed at sides of the trenches in a top layer portion of the body region; and body contact regions of the first conductive type, penetrating through the source regions in a thickness direction and contacting the body region. The body contact regions are formed in a zigzag alignment in a plan view.
    Type: Grant
    Filed: September 26, 2008
    Date of Patent: July 2, 2013
    Assignee: Rohm Co., Ltd.
    Inventor: Naoki Izumi
  • Patent number: 8426912
    Abstract: A semiconductor device according to the present invention includes: a semiconductor layer of a first conductivity type; a body region of a second conductivity type formed in a surface layer portion of the semiconductor layer; a trench dug from the surface of the semiconductor layer to penetrate the body region; a source region of a first conductivity type formed on a side portion of the trench in a surface layer portion of the body region; a gate insulating film formed on the bottom surface and the side surface of the trench; a gate electrode embedded in the trench through the gate insulating film and so formed that the surface thereof is lower by one stage than the surface of the source region; and a peripheral wall film formed on a peripheral edge portion of the surface of the gate electrode to be opposed to an upper end portion of the side surface of the trench.
    Type: Grant
    Filed: September 26, 2008
    Date of Patent: April 23, 2013
    Assignee: Rohm Co., Ltd.
    Inventor: Naoki Izumi
  • Patent number: 8384152
    Abstract: A semiconductor device includes a first conductivity type layer of a first conductivity type, a body layer of a second conductivity type formed on the first conductivity type layer, a gate trench passing through the body layer so that the deepest portion thereof reaches the first conductivity type layer, a source region of the first conductivity type formed around the gate trench on the surface layer portion of the body layer, a gate insulating film formed on the bottom surface and the side surface of the gate trench, and a gate electrode embedded in the gate trench through the gate insulating film, and the bottom surface of the gate electrode and the upper surface of the first conductivity type layer are flush with each other.
    Type: Grant
    Filed: September 19, 2008
    Date of Patent: February 26, 2013
    Assignee: Rohm Co., Ltd.
    Inventors: Yoshikazu Nakagawa, Naoki Izumi, Masaki Nagata
  • Publication number: 20120309131
    Abstract: To provide a technique that can improve the data retention characteristic of an MRAM device by improving the resistance against an external magnetic field in a semiconductor device including the MRAM device. A first magnetic shield material is disposed over a die pad via a first die attach film. Then, a semiconductor chip is mounted over the first magnetic shield material via a second die attach film. Furthermore, a second magnetic shield material is disposed over the semiconductor chip via a third die attach film. That is, the semiconductor chip is disposed so as to be sandwiched by the first magnetic shield material and the second magnetic shield material. At this time, while the planar area of the second magnetic shield material is smaller than that of the first magnetic shield material, the thickness of the second magnetic shield material is thicker than that of the first magnetic shield material.
    Type: Application
    Filed: August 10, 2012
    Publication date: December 6, 2012
    Inventors: KOJI BANDO, KAZUYUKI MISUMI, TATSUHIKO AKIYAMA, NAOKI IZUMI, AKIRA YAMAZAKI
  • Publication number: 20120267793
    Abstract: A semiconductor device wherein destruction of a sealing ring caused by cracking of an interlayer dielectric film is difficult to occur, as well as a method for manufacturing the semiconductor device, are provided. A first laminate comprises first interlayer dielectric films having a first mechanical strength. A second laminate comprises second interlayer dielectric films having a mechanical strength higher than the first mechanical strength. A first region includes first metallic layers and vias provided within the first laminate. A second region includes second metallic layers and vias provided within the second laminate. When seen in plan, the second region overlaps at least a part of the first region, is not coupled with the first region by vias, and sandwiches the second interlayer dielectric film between it and the first region.
    Type: Application
    Filed: June 27, 2012
    Publication date: October 25, 2012
    Applicant: Renesas Electronics Corporation
    Inventors: Hiroyuki Chibahara, Atsushi Ishii, Naoki Izumi, Masahiro Matsumoto
  • Publication number: 20120256246
    Abstract: A semiconductor device includes a semiconductor layer with a trench dug downward from its surface, a source region formed on a surface layer portion adjacent to a first side of the trench in a prescribed direction, a drain region formed on the surface layer portion, adjacent to a second side of the trench opposite to the first side in the prescribed direction, a first insulating film on the bottom surface and the side surface of the trench, a floating gate stacked on the first insulating film and opposed to the bottom surface and the side surface of the trench through the first insulating film, a second insulating film formed on the floating gate, and a control gate at least partially embedded in the trench so that the portion embedded in the trench is opposed to the floating gate through the second insulating film.
    Type: Application
    Filed: June 18, 2012
    Publication date: October 11, 2012
    Applicant: ROHM CO., LTD.
    Inventor: Naoki IZUMI
  • Patent number: 8269312
    Abstract: A semiconductor device according to an aspect of the present invention includes a semiconductor layer, an insulating film formed on the surface of the semiconductor layer, a first insulator embedded in the semiconductor layer with a thickness larger than the thickness of the insulating film, and a resistive element formed on the first insulator. A semiconductor device according to another aspect of the present invention includes a semiconductor layer, an insulating film formed on the surface of the semiconductor layer, a resistive element formed on the insulating film, and a floating region formed on a portion of the semiconductor layer opposed to the resistive element through the insulating film and electrically floating from a periphery thereof.
    Type: Grant
    Filed: June 3, 2009
    Date of Patent: September 18, 2012
    Assignee: Rohm Co., Ltd.
    Inventor: Naoki Izumi
  • Patent number: 8258604
    Abstract: To provide a technique that can improve the data retention characteristic of an MRAM device by improving the resistance against an external magnetic field in a semiconductor device including the MRAM device. A first magnetic shield material is disposed over a die pad via a first die attach film. Then, a semiconductor chip is mounted over the first magnetic shield material via a second die attach film. Furthermore, a second magnetic shield material is disposed over the semiconductor chip via a third die attach film. That is, the semiconductor chip is disposed so as to be sandwiched by the first magnetic shield material and the second magnetic shield material. At this time, while the planar area of the second magnetic shield material is smaller than that of the first magnetic shield material, the thickness of the second magnetic shield material is thicker than that of the first magnetic shield material.
    Type: Grant
    Filed: December 26, 2009
    Date of Patent: September 4, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Koji Bando, Kazuyuki Misumi, Tatsuhiko Akiyama, Naoki Izumi, Akira Yamazaki