Patents by Inventor Naoki Miyamoto

Naoki Miyamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040235822
    Abstract: The present invention provides a novel benzazepine derivative represented by formula: 1
    Type: Application
    Filed: February 5, 2004
    Publication date: November 25, 2004
    Inventors: Mitsuru Shiraishi, Masanori Baba, Masaki Seto, Yoshio Aramaki, Naoyuki Kanzaki, Naoki Miyamoto, Yuji Iizawa
  • Publication number: 20040228194
    Abstract: In a nonvolatile semiconductor memory in which multiple-value information is stored in one memory cell by setting a plurality of threshold values, data is successively read from word lines while continuously changing the word-line read level from a lowest level to a highest level, and the next bit line is selectively precharged in accordance with the data stored in latch means for storing read data.
    Type: Application
    Filed: June 22, 2004
    Publication date: November 18, 2004
    Inventors: Hiroshi Sato, Shoji Kubono, Toshinori Harada, Takayuki Kawahara, Naoki Miyamoto
  • Patent number: 6765840
    Abstract: In a nonvolatile semiconductor memory in which multiple-value information is stored in one memory cell by setting a plurality of threshold values, data is successively read from word lines while continuously changing the word-line read level from a lowest level to a highest level, and the next bit line is selectively precharged in accordance with the data stored in latch means for storing read data.
    Type: Grant
    Filed: February 4, 2003
    Date of Patent: July 20, 2004
    Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd., Hitachi Device Engineering Co., Ltd.
    Inventors: Hiroshi Sato, Shoji Kubono, Toshinori Harada, Takayuki Kawahara, Naoki Miyamoto
  • Publication number: 20030128604
    Abstract: In a nonvolatile semiconductor memory in which multiple-value information is stored in one memory cell by setting a plurality of threshold values, data is successively read from word lines while continuously changing the word-line read level from a lowest level to a highest level, and the next bit line is selectively precharged in accordance with the data stored in latch means for storing read data.
    Type: Application
    Filed: February 4, 2003
    Publication date: July 10, 2003
    Inventors: Hiroshi Sato, Shoji Kubono, Toshinori Harada, Takayuki Kawahara, Naoki Miyamoto
  • Patent number: 6556499
    Abstract: In a nonvolatile semiconductor memory in which multiple-value information is stored in one memory cell by setting a plurality of threshold values, data is successively read from word lines while continuously changing the word-line read level from a lowest level to a highest level, and the next bit line is selectively precharged in accordance with the data stored in latch means for storing read data.
    Type: Grant
    Filed: February 6, 2002
    Date of Patent: April 29, 2003
    Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp., Hitachi Device Engineering Co., Ltd.
    Inventors: Hiroshi Sato, Shoji Kubono, Toshinori Harada, Takayuki Kawahara, Naoki Miyamoto
  • Patent number: 6525482
    Abstract: In an ion source, a rear reflector 10 is electrically insulated from both a plasma production vessel 2 and a filament 6. The rear reflector 10 and an opposed reflector 8 are electrically connected. Further, a DC bias power supply 32 is a power supply individuated from a filament power supply 24 and an arc power supply 26. The DC bias power supply 32 is placed for applying a bias voltage VB between the opposed reflector 8 and the rear reflector 10 and the plasma production vessel 2 with both the reflectors 8 and 10 as negative potential.
    Type: Grant
    Filed: November 9, 2001
    Date of Patent: February 25, 2003
    Assignee: Nissin Electric Co., Ltd.
    Inventor: Naoki Miyamoto
  • Patent number: 6492902
    Abstract: Extraneous matter such as snow or mud sticking to an ultrasonic sensor is detected. An obstacle (10) reflects transmitted waves from an ultrasonic sensor (3), and the indirect waves (k) are received by an ultrasonic sensor (2), whereby the obstacle (10) is detected. The ultrasonic sensor (3) generates direct waves (t) directly received by the ultrasonic sensors (2) and (4), and therefore the ultrasonic sensors (2) and (4) are arranged to monitor also the direct waves (t). The direct waves (t) are attenuated when extraneous matter (8) such as snow or mud sticks to the ultrasonic sensor (4), and the presence of the extraneous matter is detected according to this attenuation.
    Type: Grant
    Filed: May 8, 2001
    Date of Patent: December 10, 2002
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yukio Nishimoto, Naoki Miyamoto
  • Publication number: 20020145599
    Abstract: There is to be provided a liquid crystal drive controller with a built-in power supply circuit wherein latch-up is made difficult to arise even if one amplitude level of the segment line drive voltage is set to the ground potential and the levels of other liquid crystal drive voltages are determined accordingly. A semiconductor integrated circuit with a built-in power supply circuit, wherein a negative voltage generated in a power supply circuit is applied to a substrate or a well region as a bias voltage, is provided with a switch for temporarily applying the ground potential to the substrate or well region to be biased with the negative voltage at the time of starting up the power supply circuit.
    Type: Application
    Filed: March 7, 2002
    Publication date: October 10, 2002
    Inventors: Kazuya Endo, Naoki Miyamoto, Toshio Mizuno, Takayuki Nakaji, Takatoshi Uchida, Kazuo Ookado, Yoshikazu Yokota
  • Publication number: 20020114183
    Abstract: In a nonvolatile semiconductor memory in which multiple-value information is stored in one memory cell by setting a plurality of threshold values, data is successively read from word lines while continuously changing the word-line read level from a lowest level to a highest level, and the next bit line is selectively precharged in accordance with the data stored in latch means for storing read data.
    Type: Application
    Filed: February 6, 2002
    Publication date: August 22, 2002
    Inventors: Hiroshi Sato, Shoji Kubono, Toshinori Harada, Takayuki Kawahara, Naoki Miyamoto
  • Publication number: 20020053880
    Abstract: In an ion source, a rear reflector 10 is electrically insulated from both a plasma production vessel 2 and a filament 6. The rear reflector 10 and an opposed reflector 8 are electrically connected. Further, a DC bias power supply 32 is a power supply individuated from a filament power supply 24 and an arc power supply 26. The DC bias power supply 32 is placed for applying a bias voltage VB between the opposed reflector 8 and the rear reflector 10 and the plasma production vessel 2 with both the reflectors 8 and 10 as negative potential.
    Type: Application
    Filed: November 9, 2001
    Publication date: May 9, 2002
    Applicant: NISSIN ELECTRIC CO., LTD.
    Inventor: Naoki Miyamoto
  • Patent number: 6385085
    Abstract: In a nonvolatile semiconductor memory in which multiple-value information is stored in one memory cell by setting a plurality of threshold values, data is successively read from word lines while continuously changing the word-line read level from a lowest level to a highest level, and the next bit line is selectively precharged in accordance with the data stored in latch means for storing read data.
    Type: Grant
    Filed: April 10, 2001
    Date of Patent: May 7, 2002
    Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp., Hitachi Device Engineering Co., Ltd.
    Inventors: Hiroshi Sato, Shoji Kubono, Toshinori Harada, Takayuki Kawahara, Naoki Miyamoto
  • Publication number: 20020047780
    Abstract: Extraneous matter such as snow or mud sticking to ultrasonic sensor is detected. An obstacle 10 reflects transmitted waves from an ultrasonic sensor 3, and the indirect waves k are received by an ultrasonic sensor 2, whereby the obstacle 10 is detected. The ultrasonic sensor 3 generates direct waves t directly received by the ultrasonic sensors 2 and 4, and therefore the ultrasonic sensors 2 and 4 are arranged to monitor also the direct waves t. The direct waves t are attenuated when extraneous matter 8 such as snow or mud sticks to the ultrasonic sensor 4, and the presence of the extraneous matter is detected according to this attenuation.
    Type: Application
    Filed: May 8, 2001
    Publication date: April 25, 2002
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Yukio Nishimoto, Naoki Miyamoto
  • Publication number: 20010015909
    Abstract: In a nonvolatile semiconductor memory in which multiple-value information is stored in one memory cell by setting a plurality of threshold values, data is successively read from word lines while continuously changing the word-line read level from a lowest level to a highest level, and the next bit line is selectively precharged in accordance with the data stored in latch means for storing read data.
    Type: Application
    Filed: April 10, 2001
    Publication date: August 23, 2001
    Inventors: Hiroshi Sato, Shoji Kubono, Toshinori Harada, Takayuki Kawahara, Naoki Miyamoto
  • Patent number: 6222763
    Abstract: In a nonvolatile semiconductor memory in which multiple-value information is stored in one memory cell by setting a plurality of threshold values, data is successively read from word lines while continuously changing the word-line read level from a lowest level to a highest level, and the next bit line is selectively precharged in accordance with the data stored in latch means for storing read data.
    Type: Grant
    Filed: February 3, 2000
    Date of Patent: April 24, 2001
    Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp., Hitachi Device Engineering Co., Ltd.
    Inventors: Hiroshi Sato, Shoji Kubono, Toshinori Harada, Takayuki Kawahara, Naoki Miyamoto
  • Patent number: 6026014
    Abstract: In a nonvolatile semiconductor memory in which multiple-value information is stored in one memory cell by setting a plurality of threshold values, data is successively read from word lines while continuously changing the word-line read level from a lowest level to a highest level, and the next bit line is selectively precharged in accordance with the data stored in latch means for storing read data.
    Type: Grant
    Filed: December 19, 1997
    Date of Patent: February 15, 2000
    Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp., Hitachi Device Engineering Co., Ltd.
    Inventors: Hiroshi Sato, Shoji Kubono, Toshinori Harada, Takayuki Kawahara, Naoki Miyamoto
  • Patent number: 5694358
    Abstract: This invention provides a nonvolatile semiconductor memory device having a word line, a plurality of bit lines crossing the word line, and a plurality of memory cells including MOS transistors. Each of control gates of the MOS transistors are coupled to the word line and each of drains thereof are coupled to the bit lines, respectively. Each of the MOS transistors also has a floating gate. Further, the non-volatile semiconductor memory device comprises latch circuits, first switches, a sense amplifier coupled to the plurality of bit lines in common, and second switches. The latch circuits are coupled to the plurality of bit lines through the first switches which are coupled between the plurality of bit lines and the latch circuits, respectively. The second switches are respectively coupled between the plurality of bit lines and the sense amplifier, thereby coupling the sense amplifier to the bit lines.
    Type: Grant
    Filed: September 24, 1996
    Date of Patent: December 2, 1997
    Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.
    Inventors: Takayuki Kawahara, Yusuke Jyouno, Syunichi Saeki, Naoki Miyamoto, Katsutaka Kimura
  • Patent number: 5205950
    Abstract: The present invention provides a process for preparing iron carbide fine particles having an average particle size (long axis) of 0.1 to 2 .mu.m and an average axial ratio of 3 to 20, which comprises,(a) optionally contacting an iron compound selected from the group consisting of iron oxyhydroxide fine particles and iron oxide fine particles with a reducing agent which does not contain carbon atom, the iron compound being, prior to the above contact, coated with iron compound or iron compound and cobalt compound, and with aluminum compound or silicon compound, and(b) contacting the iron compound of the above (a) with a reducing-and-carburizing agent containing carbon atom or a mixture thereof with a reducing agent which does not contain carbon atom.
    Type: Grant
    Filed: July 1, 1991
    Date of Patent: April 27, 1993
    Assignee: Daikin Industries, Ltd.
    Inventors: Yoshiyuki Shibuya, Naoki Miyamoto, Shigeo Daimon
  • Patent number: 5171398
    Abstract: Disclosed herein is an equipment for sticking a vinyl tape on the backside surface of a wafer prior to the dicing of the wafer. Suction ports for sucking and supporting the peripheral part of the wafer surface is provided in the outer block of a stage for supporting the wafer, a recessed part is formed at the central part of the support stage so as to avoid the contact of the central part of the wafer to the support stage, and concentric ring-shaped projection parts are formed on the bottom surface of the recessed part. The height of the top face of the ring-shaped projection parts is set to be slightly lower than the outer block of the support stage which is the wafer contact part, with minute gaps being kept from the fixed wafer. It is possible to prevent the generation of flexure due to a turning roller at the time of sticking of the tape by introducing high pressure air to the recessed part of the wafer support part and the minute gaps.
    Type: Grant
    Filed: October 19, 1990
    Date of Patent: December 15, 1992
    Assignee: NEC Corporation
    Inventor: Naoki Miyamoto