Abstract: A layer planarizing method for a semiconductor device is provided to attain excellent controllability of a polishing amount to form a uniform and flat layer without uniformity in polishing in a wafer surface. According to the method, a first layer is deposited over at least a top portion of a stepped portion formed on a surface of a body, the stepped portion covered with the first layer is covered with a second layer having a higher polishing rate than that of the first layer, and the second layer is polished until the first layer deposited on the top portion of the stepped portion is exposed.

Abstract: A method of planarizing films in a semiconductor device, which is capable of uniformly planarizing films at a good controllability in polished amounts while keeping uniformity in polishing within a wafer surface. The method includes the steps of forming a first film on at least a step portion provided on a base body, covering the step portion with a second film containing phosphorus in an amount of from 6 to 9 wt % and higher in polishing rate than the first film, and polishing the second film to expose the first film formed on the top of the step portion.

Abstract: A layer planarizing method for a semiconductor device is provided to attain excellent controllability of a polishing amount to form a uniform and flat layer on a non-uniform wafer in polishing in a wafer surface. According to the method, a first layer is deposited over at least a top portion of a stepped portion formed on a surface of a body, the stepped portion covered with the first layer is covered with a second layer having a higher polishing rate than that of the first layer, and the second layer is polished until the first layer deposited on the top portion of the stepped portion is exposed.

Abstract: Transistor devices comprise a gate electrode, a channel region formed beneath the gate electrode, a source region in contact with one side of the channel region, a first conductive region formed in a semiconductor layer at the outer side of the source region and made of a metal or metal compound, a drain region formed in contact with the other side of the channel region, and a second conductive region formed in the semiconductor layer at the outer side of the drain region and consisting of a metal or a metal compound. The transistor has an SOI structure which has an improved breakdown voltage between the source region and the drain region with low sheet resistances of the source and drain regions. Methods for making the transistor devices are also described.

Abstract: The disclosure relates to a method of forming a multilayer interconnection structure. The structure is a laminated body having a first conductive layer, a first insulating layer, a second conductive layer and a second insulating layer in an ascending order. In the method, firstly, a through-hole is formed on the laminated body so as to expose a surface of the first conductive layer and two opposed surfaces of the second conductive layer. Then, the two opposed surfaces of the second conductive layer is masked with a masking film, so as not to deposit thereon a conductive material which has a strong and selective adhesion on the first and second conductive layers. Then, the conductive material is deposited on the surface of the first conductive layer by a chemical vapor deposition method so as to fill a lower portion of the through-hole with the conductive material. Then, the masking film is removed so as to expose the two opposed surfaces of the second conductive layer.

Abstract: The disclosure relates to a method of forming a multilayer interconnection structure. The structure is a laminated body having a first conductive layer, a first insulating layer, a second conductive layer and a second insulating layer in an ascending order. In the method, firstly, a through-hole is formed on the laminated body so as to expose a surface of the first conductive layer and two opposed surfaces of the second conductive layer. Then, the two opposed surfaces of the second conductive layer is masked with a masking film, so as not to deposit thereon a metal which has a strong and selective adhesion on the first and second conductive layers. Then, the metal is deposited on the surface of the first conductive layer by a chemical vapor deposition method so as to fill a lower portion of the through-hole with the metal. Then, the masking film is removed so as to expose the two opposed surfaces of the second conductive layer.