Patents by Inventor Naoki Nojiri

Naoki Nojiri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040001869
    Abstract: The present invention provides a cosmetic composition having excellent application feeling and a transparency while maintaining covering power. The cosmetic composition comprises (a) composite particles obtained by allowing at least two kinds of particles having different shapes and particle diameters to contact at least one kind of polymer compounds selected from fluorinated polymer compounds, silicone polymer compounds, and mixture thereof in the presence of supercritical carbon dioxide, and (b) cosmetic components.
    Type: Application
    Filed: April 10, 2003
    Publication date: January 1, 2004
    Inventors: Yuko Yago, Keisuke Nakao, Ryuji Hasegawa, Noboru Nagatani, Keiichi Fukuda, Naoki Nojiri, Hidetake Nakamura, Hideaki Kubo
  • Publication number: 20030215572
    Abstract: A process for preparing composite particles having a coating of an organic compound on their surfaces, comprising the steps of (a) dissolving an organic compound in supercritical carbon dioxide to give an organic compound solution; (b) contacting particles which do not dissolve in the supercritical carbon dioxide with the organic compound solution in a vessel; and (c) reducing the internal pressure of the vessel at an internal temperature of not less than the critical temperature of carbon dioxide. The composite particles have controlled properties such as water repellency, oil repellency, optical properties, ultraviolet shielding ability, texture, safety, activity, color tone, stability of dispersion and weatherproof, which can be suitably used for paints, ink-jet ink and cosmetics, and the composite particles obtained.
    Type: Application
    Filed: April 11, 2003
    Publication date: November 20, 2003
    Inventors: Naoki Nojiri, Takuya Imaki, Hideaki Kubo, Hidetake Nakamura
  • Publication number: 20030011418
    Abstract: In a CMOS level shifting circuit including N-channel transistors that have sources to which a digital signal is supplied, a bias voltage Vref is supplied to gates of the N-channel transistors, and the bias voltage Vref is set to be higher than a high level voltage of the digital signal and lower than a value obtained by adding a threshold voltage of the N-channel transistors to the high level voltage of the digital signal. Thus, a level shifting circuit is provided that is capable of outputting a signal having subjected to stable level conversion, even when a voltage level of a low voltage signal is lowered.
    Type: Application
    Filed: July 10, 2002
    Publication date: January 16, 2003
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hidetoshi Nishimura, Masahiro Gion, Heiji Ikoma, Naoki Nojiri
  • Patent number: 6489689
    Abstract: Two NMOS transistors and two PMOS transistors are provided on a substrate. Power supply lines VDD and VSS connected to the transistors are provided in the second wiring layer. A metal line is provided in the third wiring layer, which is the uppermost wiring layer, and the pad is connected to the metal line. Even when the width of the metal line is increased so as to increase the acceptable current capacity thereof, it is possible to keep the wiring area ratio of the first wiring layer in the I/O region at a low level. Thus, it is possible to suppress the global step between the I/O region and the central region of the chip.
    Type: Grant
    Filed: May 29, 2001
    Date of Patent: December 3, 2002
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Naoki Nojiri
  • Patent number: 6445210
    Abstract: In a level shifter including a latch consisting of two p-channel transistors P1 and P2, when an input signal at a terminal IN changes from H- into L-level, an n-channel transistor N2 turns ON, thereby dropping a potential level at a node W2. However, since a p-channel transistor P4 is OFF, no short-circuit current flows from a high voltage supply VDD3 into the ground by way of the transistors P2 and N2. On the other hand, since n- and p-channel transistors N1 and P3 are OFF, both terminals of a node W1 are electrically isolated. But the high voltage supply VDD3 pulls the node W1 up to a high voltage level by way of the p-channel transistors P4 and P1 and another p-channel transistor P5 as a resistor. Accordingly, the capacitance to be driven by the n-channel transistors N1 and N2 can be reduced, thus shortening the delay.
    Type: Grant
    Filed: February 7, 2001
    Date of Patent: September 3, 2002
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Naoki Nojiri
  • Publication number: 20020041927
    Abstract: A process for preparing composite particles comprising particles and an organic compound in a vessel, comprising the steps of (a) contacting particles with an organic compound in the presence of supercritical carbon dioxide or liquefied carbon dioxide in the vessel; and (b) reducing the internal pressure of the vessel. The composite particles have controlled properties such as water repellency, oil repellency, optical properties, ultraviolet shielding ability, texture, safety, activity, color tone, stability of dispersion and weatherproof, which can be suitably used for paints, ink-jet ink and cosmetics, and the composite particles obtained.
    Type: Application
    Filed: October 10, 2001
    Publication date: April 11, 2002
    Inventors: Naoki Nojiri, Takuya Imaki, Hideaki Kubo, Hidetake Nakamura
  • Publication number: 20010045670
    Abstract: Two NMOS transistors and two PMOS transistors are provided on a substrate. Power supply lines VDD and VSS connected to the transistors are provided in the second wiring layer. A metal line is provided in the third wiring layer, which is the uppermost wiring layer, and the pad is connected to the metal line. Even when the width of the metal line is increased so as to increase the acceptable current capacity thereof, it is possible to keep the wiring area ratio of the first wiring layer in the I/O region at a low level. Thus, it is possible to suppress the global step between the I/O region and the central region of the chip.
    Type: Application
    Filed: May 29, 2001
    Publication date: November 29, 2001
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventor: Naoki Nojiri
  • Publication number: 20010013795
    Abstract: In a level shifter including a latch consisting of two p-channel transistors P1 and P2, when an input signal at a terminal IN changes from H- into L-level, an n-channel transistor N2 turns ON, thereby dropping a potential level at a node W2. However, since a p-channel transistor P4 is OFF, no short-circuit current flows from a high voltage supply VDD3 into the ground by way of the transistors P2 and N2. On the other hand, since n- and p-channel transistors N1 and P3 are OFF, both terminals of a node W1 are electrically isolated. But the high voltage supply VDD3 pulls the node W1 up to a high voltage level by way of the p-channel transistors P4 and P1 and another p-channel transistor P5 as a resistor. Accordingly, the capacitance to be driven by the n-channel transistors N1 and N2 can be reduced, thus shortening the delay.
    Type: Application
    Filed: February 7, 2001
    Publication date: August 16, 2001
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventor: Naoki Nojiri
  • Patent number: 6168719
    Abstract: To provide a method for purification of the ionic polymer compound comprising efficiently removing low-molecular impurities, for example, ionic remaining monomers, which are charged identically to the ionic polymer compound from the ionic polymer compound in a shorter period of time. A method for purification of an ionic polymer compound, characterized by removing low-molecular impurities, such as ionic remaining monomers, by the use of an ultrafiltration membrane and/or a reverse osmosis membrane from an aqueous solution containing the ionic polymer compound and low-molecular impurities which are charged identically to the ionic polymer compound, under conditions that a concentration of the ionic polymer compound is from 7 to 20% by weight, and that an amount of charges of the ionic polymer compound in the aqueous solution is 0.30 gram-equivalent/liter or more.
    Type: Grant
    Filed: June 25, 1999
    Date of Patent: January 2, 2001
    Assignee: Kao Corporation
    Inventors: Keishi Shimokawa, Takuya Imaki, Jun Shida, Naoki Nojiri, Shinobu Hiramatsu