Abstract: The present invention relates to a process for producing a decrystallized cellulose having a reduced cellulose I-type crystallinity from a cellulose-containing raw material in an efficient manner with an excellent productivity. In accordance with the present invention, there is provided a process for producing a decrystallized cellulose from a raw material comprising at least 20% by weight, based on the weight of the raw material excluding water contained therein, of a cellulose having a cellulose I-type crystallinity of more than 33% as calculated from the following formula: Cellulose I-type Crystallinity (%)=[(I22.6?I18.5)/I22.6]×100 wherein I22.6 is a diffraction intensity of a lattice plane (002 plane) as measured at a diffraction angle 2? of 22.6° in X-ray diffraction analysis; and I18.5 is a diffraction intensity of an amorphous moiety as measured at a diffraction angle 2? of 18.

Abstract: The invention relates to a highly productive process for producing decrystallized cellulose which includes treating a cellulose-containing raw material by means of a mill, wherein the cellulose-containing raw material has a cellulose content of a residue obtained by removing water from the cellulose-containing raw material of 20 mass % or more, has a cellulose I-type crystallinity of cellulose more than 33% as calculated from the following formula (1): Cellulose I-type Crystallinity (%)=[(I22.6?I18.5)/I22.6]×100??(1), wherein I22.6 is a diffraction intensity of a lattice plane (002 plane) as measured at a diffraction angle 2? of 22.6° in X-ray diffraction analysis; and I18.5 is a diffraction intensity of an amorphous moiety as measured at a diffraction angle 2? of 18.5° in X-ray diffraction analysis, and has a water content of 1.8 mass % or less, to thereby reduce the cellulose I-type crystallinity to 33% or less.

Abstract: A delay simulation system comprises an input unit configured to input a netlist, a library, and information including load capacitances; and a simulation unit; the library defines a plurality of distortion patterns of input waveforms of the cells and defines delay values in correspondence with the plurality of distortion patterns of the input waveforms, slopes of the input waveforms, and the load capacitances; and the simulating unit is configured to calculate the delay time in such a manner that the simulating unit selects a distortion pattern of an input waveform according to a logic state of the cell, obtains a slope of the input waveform based on a load capacitance, and obtains a delay value corresponding to the distortion pattern of the input waveform, the slope of the input waveform and the load capacitance, from the library.

Abstract: A process for producing saccharide, including saccharifying decrystallized cellulose prepared from a raw material containing cellulose having cellulose I-type crystallinity of more than 33%, the process including: treating the cellulose-containing raw material by means of a mill to reduce the cellulose I-type crystallinity of the cellulose to 33% or less, wherein the cellulose-containing raw material has a cellulose content of a residue obtained by removing water from the cellulose-containing raw material of 20% by weight or more, to thereby prepare decrystallized cellulose, and causing a cellulase and/or a hemicellulase to act on the decrystallized cellulose.

Abstract: The present invention relates to a process for producing a cellulose ether derivative in an industrially convenient and efficient manner by reacting a low-crystalline powdery cellulose with an epoxy compound in the presence of a catalyst.

Abstract: In a level shift circuit, the threshold voltage of N-type high-voltage transistors, to whose gates the voltage of a low-voltage supply VDD is applied, is set low. An input signal IN powered by the low-voltage supply VDD is input to the gate of an N-type transistor by way of an inverter. Therefore, even if the potentials at nodes W3 and W4 exceed the voltage of the low-voltage supply VDD, reverse current flow from the nodes W3 and W4 via parasitic diodes within the inverters into the low-voltage supply VDD is prevented. A protection circuit, composed of N-type transistor whose respective gates are fixed to the low-voltage supply VDD, is disposed between the two N-type high-voltage transistors N5, N6 and two N-type low-voltage transistors N1, N2 for receiving the complementary signals IN and XIN, thereby preventing the breakdown of those N-type complementary-signal-receiving transistors.

Abstract: The present invention relates to a process for producing a decrystallized cellulose having a reduced cellulose I-type crystallinity from a cellulose-containing raw material in an efficient manner with an excellent productivity. In accordance with the present invention, there is provided a process for producing a decrystallized cellulose from a raw material containing a cellulose having a cellulose I-type crystallinity of more than 33% as calculated from the following formula: Cellulose I-type Crystallinity (%)=[(I22.6?I18.5)/I22.6]×100 wherein I22.6 is a diffraction intensity of a lattice plane (002 plane) as measured at a diffraction angle 2? of 22.6° in X-ray diffraction analysis; and I18.5 is a diffraction intensity of an amorphous moiety as measured at a diffraction angle 2? of 18.

Abstract: In a level shifter, OFF leakage currents flow through two N-type transistors for signal input even when they are OFF. However, another N-type transistor serving as an OFF leakage generation circuit and three P-type transistors serving as current mirrors, which constitute a current conversion circuit, supply to the signal-input transistors a current equivalent to or greater than the OFF leakage currents flowing through the signal-input transistors when they are OFF, thereby canceling the OFF leakage currents. Therefore, one of nodes which is at H level is surely fixed to a potential equal to a higher voltage supply. Thus, the level shifter surely operates with a high speed even when large OFF leakage currents flow through the signal-input transistors.

Abstract: In a level shift circuit, the threshold voltage of N-type high-voltage transistors, to whose gates the voltage of a low-voltage supply VDD is applied, is set low. An input signal IN powered by the low-voltage supply VDD is input to the gate of an N-type transistor by way of an inverter. Therefore, even if the potentials at nodes W3 and W4 exceed the voltage of the low-voltage supply VDD, reverse current flow from the nodes W3 and W4 via parasitic diodes within the inverters into the low-voltage supply VDD is prevented. A protection circuit, composed of N-type transistor whose respective gates are fixed to the low-voltage supply VDD, is disposed between the two N-type high-voltage transistors N5, N6 and two N-type low-voltage transistors N1, N2 for receiving the complementary signals IN and XIN, thereby preventing the breakdown of those N-type complementary-signal-receiving transistors.

Abstract: In a level shifter, OFF leakage currents flow through two N-type transistors for signal input even when they are OFF. However, another N-type transistor serving as an OFF leakage generation circuit and three P-type transistors serving as current mirrors, which constitute a current conversion circuit, supply to the signal-input transistors a current equivalent to or greater than the OFF leakage currents flowing through the signal-input transistors when they are OFF, thereby canceling the OFF leakage currents. Therefore, one of nodes which is at H level is surely fixed to a potential equal to a higher voltage supply. Thus, the level shifter surely operates with a high speed even when large OFF leakage currents flow through the signal-input transistors.

Abstract: In a level shifter, OFF leakage currents flow through two N-type transistors for signal input even when they are OFF. However, another N-type transistor serving as an OFF leakage generation circuit and three P-type transistors serving as current mirrors, which constitute a current conversion circuit, supply to the signal-input transistors a current equivalent to or greater than the OFF leakage currents flowing through the signal-input transistors when they are OFF, thereby canceling the OFF leakage currents. Therefore, one of nodes which is at H level is surely fixed to a potential equal to a higher voltage supply. Thus, the level shifter surely operates with a high speed even when large OFF leakage currents flow through the signal-input transistors.

Abstract: In a level shift circuit, the threshold voltage of N-type high-voltage transistors, to whose gates the voltage of a low-voltage supply VDD is applied, is set low. An input signal IN powered by the low-voltage supply VDD is input to the gate of an N-type transistor by way of an inverter. Therefore, even if the potentials at nodes W3 and W4 exceed the voltage of the low-voltage supply VDD, reverse current flow from the nodes W3 and W4 via parasitic diodes within the inverters into the low-voltage supply VDD is prevented. A protection circuit, composed of N-type transistor whose respective gates are fixed to the low-voltage supply VDD, is disposed between the two N-type high-voltage transistors N5, N6 and two N-type low-voltage transistors N1, N2 for receiving the complementary signals IN and XIN, thereby preventing the breakdown of those N-type complementary-signal-receiving transistors.

Abstract: A cosmetic composition having excellent application feeling and transparency while maintaining covering power which includes (a) composite particles obtained by allowing at least two kinds of particles having different shapes and particle diameters to contact with at least one polymer compound selected from the group consisting of fluorinated polymer compounds, silicone polymer compounds, and mixture thereof, in the presence of supercritical carbon dioxide, and (b) a cosmetic component.

Abstract: In a level shifter, OFF leakage currents flow through two N-type transistors for signal input even when they are OFF. However, another N-type transistor serving as an OFF leakage generation circuit and three P-type transistors serving as current mirrors, which constitute a current conversion circuit, supply to the signal-input transistors a current equivalent to or greater than the OFF leakage currents flowing through the signal-input transistors when they are OFF, thereby canceling the OFF leakage currents. Therefore, one of nodes which is at H level is surely fixed to a potential equal to a higher voltage supply. Thus, the level shifter surely operates with a high speed even when large OFF leakage currents flow through the signal-input transistors.

Abstract: In an I/O circuit unit located in the periphery of a semiconductor chip, a plurality of ESD protection transistors are provided in each I/O cell. An electrode pad cell has a two-layer structure including a lower electrode pad and an upper electrode pad. The electrode pad cell is arranged so as to be present over a connection line of ESD protection transistors of an associated I/O cell. With part of the first pad portion of an adjacent electrode pad located in an end portion of the second pad portion of the electrode pad, the second pad portion can not extend further onward but the third pad portion having a smaller width than that of the second pad portion is arranged onward. Thus, destruction of the ESD protection transistors is not caused, so that an internal circuit is protected from an electrostatic discharge which comes into electrode pads.

Abstract: In a level shift circuit, the threshold voltage of N-type high-voltage transistors, to whose gates the voltage of a low-voltage supply VDD is applied, is set low. An input signal IN powered by the low-voltage supply VDD is input to the gate of an N-type transistor by way of an inverter. Therefore, even if the potentials at nodes W3 and W4 exceed the voltage of the low-voltage supply VDD, reverse current flow from the nodes W3 and W4 via parasitic diodes within the inverters into the low-voltage supply VDD is prevented. A protection circuit, composed of N-type transistor whose respective gates are fixed to the low-voltage supply VDD, is disposed between the two N-type high-voltage transistors N5, N6 and two N-type low-voltage transistors N1, N2 for receiving the complementary signals IN and XIN, thereby preventing the breakdown of those N-type complementary-signal-receiving transistors.

Abstract: According to the invention, in input/output circuit portions positioned around a semiconductor chip, electrode pads are arranged above each of a plurality of input/output cells arranged in a line. The width of the electrode pads is greater than the width of the input/output cells, and thus the electrode pads cannot be arranged in a single line and are instead arranged staggered in two lines. The electrode pads of one row are arranged shifted so that they do not overlap with the internal terminals of the input/output cells, but are disposed near these internal terminals. The spacing between the electrode pads is set to a distance that is at least a set distance determined by the isolation rules of the design.

Abstract: In an I/O circuit unit located in the periphery of a semiconductor chip, a plurality of ESD protection transistors are provided in each I/O cell. An electrode pad cell has a two-layer structure including a lower electrode pad and an upper electrode pad. The electrode pad cell is arranged so as to be present over a connection line of ESD protection transistors of an associated I/O cell. With part of the first pad portion of an adjacent electrode pad located in an end portion of the second pad portion of the electrode pad, the second pad portion can not extend further onward but the third pad portion having a smaller width than that of the second pad portion is arranged onward. Thus, destruction of the ESD protection transistors is not caused, so that an internal circuit is protected from an electrostatic discharge which comes into electrode pads.

Abstract: According to the invention, in input/output circuit portions positioned around a semiconductor chip, electrode pads are arranged above each of a plurality of input/output cells arranged in a line. The width of the electrode pads is greater than the width of the input/output cells, and thus the electrode pads cannot be arranged in a single line and are instead arranged staggered in two lines. The electrode pads of one row are arranged shifted so that they do not overlap with the internal terminals of the input/output cells, but are disposed near these internal terminals. The spacing between the electrode pads is set to a distance that is at least a set distance determined by the isolation rules of the design.

Abstract: In a CMOS level shifting circuit including N-channel transistors that have sources to which a digital signal is supplied, a bias voltage Vref is supplied to gates of the N-channel transistors, and the bias voltage Vref is set to be higher than a high level voltage of the digital signal and lower than a value obtained by adding a threshold voltage of the N-channel transistors to the high level voltage of the digital signal. Thus, a level shifting circuit is provided that is capable of outputting a signal having subjected to stable level conversion, even when a voltage level of a low voltage signal is lowered.