Abstract: A thread processing method that is executed by a multi-core processor, includes supplying a command to execute a first thread to a first processor; judging a dependence relationship between the first thread and a second thread to be executed by a second processor; comparing a first threshold and a frequency of access of any one among shared memory and shared cache memory by the first thread; and changing a phase of a first operation clock of the first processor when the access frequency is greater than the first threshold and upon judging that no dependence relationship exists.

Abstract: A thread processing method is executed by a specific apparatus included among a plurality of apparatuses, and includes assigning one thread among a plurality of threads to the apparatuses, respectively; acquiring first time information that indicates a time at which the specific apparatus receives an execution result of a corresponding thread from each of the apparatuses; and setting a priority level of an access right to access shared memory that is shared by the apparatuses and the specific apparatus, the setting being based on the first time information and second time information that indicates a time at which reception of execution results of the threads from the apparatuses ends.

Abstract: A data allocation method executed by a data allocation system. The data allocation method includes allocating to a first processing apparatus included among a plurality of processing apparatuses and allocating based on a first communication speed of the first processing apparatus, data having communication amount information on a frequency at which the processing apparatuses access the data, and further supplying first priority level information to the first processing apparatus; and exchanging based on variation of a communication speed of at least one processing apparatus among the processing apparatuses, the data or the first priority level information, and data or second priority level information allocated to a second processing apparatus included among the processing apparatuses and having a second communication speed.

Abstract: A scheduling method is executed by a first apparatus among a plurality of apparatuses. The scheduling method includes assigning a process to at least one apparatus among the apparatuses based on a first table that includes each communication strength of the apparatuses; receiving an execution result of the process and a communication strength from the at least one apparatus; and creating the first table based on the received communication strength.

Abstract: A data processing method is executed by a first device, and includes suspending execution of a first process by the first device that belongs to a first device group that includes plural devices; saving based on a request for execution of a second process from a second device that belongs to a second device group that includes plural devices, process information of the first process to shared memory that is set in each of the devices of the first device group and shared by the devices of the first device group; and releasing the saving of the process information of the first process consequent to completion of the execution of the second process.

Abstract: A scheduling method that is executed by a first device includes acquiring in response to a process request received by the first device, any one among a device count of peripheral devices near the first device and a device count of the peripheral devices near the first device, including the first device; and determining, by a CPU of the first device, a scheduling method for scheduling a process corresponding to the process request, based on the device count.

Abstract: An exclusive access control method is executed by a computer having an operating system that when an excluded thread accesses a shared resource, executes a first exclusive access control process of prohibiting the excluded thread from attempting to access the shared resource until exclusive access control is released, the exclusive access control process being executed according to a number of attempts, by the excluded thread, to access the shared resources. The exclusive access control method includes counting by at least one second thread, including the excluded thread and different from a first thread, the number of attempts to access the shared resource, when the first thread executes a second exclusive access control process of allowing the excluded thread to attempt to access the shared resource until the excluded thread is permitted access; and storing to a memory area by the second thread, the counted number of attempts.

Abstract: A multi-core processor system includes plural CPUs; memory that is shared among the CPUs; and a monitoring unit that instructs a change of assignment of threads to the CPUs based on a first process count stored in the memory and representing a count of processes under execution by the CPUs and a second process count representing a count of processes assigned to the CPUs, respectively.

Abstract: An endian conversion method is executed by a CPU, and includes executing a program that includes endian conversion setting; and performing, when accessing an address of a main memory indicated in the endian conversion setting, endian conversion of data specified by the address of the main memory.

Abstract: A file sharing method executed by a first terminal, and including selecting from among multiple terminals including the first terminal and based on a remaining battery level of the terminals and a processing time of a shared process, a second terminal to execute the shared process for sharing multiple files among the terminals; and assigning the shared process to the second terminal.

Abstract: A scheduling method is executed by a first CPU and a second CPU. The scheduling method includes acquiring by the first CPU and when a first application is invoked, a first threshold for executing the first application; transmitting by the first CPU, a first threshold to the second CPU; and giving notification to the first CPU by the second CPU when an execution capability of the second CPU is greater than or equal to the first threshold, the notification indicating that the second CPU can execute the first application. The second CPU does not give notification to the first CPU when the execution capability of the second CPU is less than the first threshold.

Abstract: A task scheduling method is executed by a multi-core system and includes reading from a profile memory, first information concerning operation of a first task in a single core system; calculating second information concerning operation of a second task in the multi-core system, based on the first information; and setting based on the second information, an operating environment of a core that executes the second task.

Abstract: A scheduling method is executed by a processor, and includes detecting a transition from a first process to a second process; acquiring from memory, an operating frequency and a CPU count for executing the second process; suspending a CPU under operation or starting a suspended CPU, based on the CPU count; and assigning the operating frequency to a CPU that is to execute the second process.

Abstract: A system includes plural processors; memory that stores a program currently under execution by the processors; and a pre-loader that pre-loads into a fragment area of the memory, a target program that is to be executed and is a program other than the program currently under execution by the processors.

Abstract: A scheduling method is executed by a given CPU among multiple CPUs. The scheduling method includes subtracting for each of the CPUs, a number of processes assigned to the CPU from a maximum number of speculative processes that can be assigned to each of the CPUs; summing results yielded at the subtracting to yield a total number of speculative processes; and assigning to the CPUs, speculative processes of a number is less than or equal to the total number of speculative processes.

Abstract: A multi-task scheduling method includes assigning a first thread to a first processor; detecting a second thread that is executed after the first thread; calculating based on a load of a processor that is assigned a third thread that generates the second thread, a first time that lasts until a start of the second thread; calculating a second time that lasts until completion of execution of the first thread; and changing a first time slice of the first processor to a second time slice when the second time is greater than the first time.

Abstract: A multi-core processor system includes plural processors; and a scheduler that assigns applications to the processors. The scheduler upon receiving a startup request for a given application and based on start times of the applications executed by the processors, selects a processor that is to execute the given application.

Abstract: A multicore processor system includes multiple processors; a device; a memory that stores information of voltage and clock frequency for minimizing power consumption in connection with a number of the processors accessing to the device; and a power control unit that controls the voltage and the clock frequency of the processors on the basis of the information stored in the memory if the number of the processors accessing to the device changes.

Abstract: A signal processing circuit is configured by connecting a plurality of basic circuits connected in series, each of the basic circuits comprising an arithmetic circuit subjecting a first input signal and a second input signal to a signal processing; a first selection circuit outputting the first input signal or an output signal of the arithmetic circuit; and a second selection circuit outputting the second input signal or an output signal of the arithmetic circuit, so as to make it possible to change operations of the circuit as a whole by properly making a selection on which signal should be output with the aid of the first and second selection circuits, and to execute different signal processing on a single circuit depending on the selection.

Abstract: A reconfigurable LSI which can actualize a plurality of functions by reconfiguration based on configuration information, comprises at least a plurality of arithmetic processing modules, has state information for indicating the transition of the function from a previous state to a next state, transition condition information for indicating the condition for transitioning from the previous state to the next state, and output information for switching the connection between the arithmetic processing module corresponding to the transition condition and the data network connected to the arithmetic processing module, and has a reconfiguration control circuit which transmits the output information corresponding to the next state to a selector for switching between the arithmetic processing module and the data network when the conditions for transition are received from the arithmetic processing module and matches the condition of the transition condition information.