Patents by Inventor Naoki Sano

Naoki Sano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20020196424
    Abstract: A distance measuring apparatus controls a forward laser beam to scan a detection area. A photodetector array includes a plurality of photo detecting elements. At least one is selected among the photo detecting elements as an effective element, and the effective element is changed from one to another in response to the direction of the forward laser beam. Identification is given of at least one among the photo detecting elements which receives an echo laser beam corresponding to the forward laser beam in a specified direction. An actual correspondence relation between directions of the forward laser beam and the photo detecting elements receiving corresponding echo laser beams is grasped on the basis of a relation between the identified photo detecting element and the specified direction. The selection and change of the effective element are executed according to the grasped actual correspondence relation.
    Type: Application
    Filed: June 20, 2002
    Publication date: December 26, 2002
    Inventors: Naoki Sano, Emiko Isogai, Ryoichi Sugawara
  • Patent number: 6458715
    Abstract: A target semiconductor device can be obtained stably by reforming an insulating film and a semiconductor. In a process of manufacturing a semiconductor device, at least one of the semiconductor and the insulating film is reformed after an annealing process for annealing the semiconductor at a temperature ranging from 20 to 400° C. in the atmosphere containing a gas of water (H2O) with a partial pressure from 1 Torr to a saturated vapor pressure for an annealing time ranging from 15 seconds to 20 hours.
    Type: Grant
    Filed: February 8, 2001
    Date of Patent: October 1, 2002
    Assignee: Sony Corporation
    Inventors: Naoki Sano, Masaki Hara, Mitsunobu Sekiya, Toshiyuki Sameshima
  • Patent number: 6400448
    Abstract: A photo detecting device includes an output line leading to a processing circuit, and an array of pixels including respective photo detecting zones for changing incident light into corresponding electric signals through photoelectric conversion. Each of the pixels includes a first switch for selectively connecting and disconnecting a related photo detecting zone to and from the output line, and a second switch for selectively connecting and disconnecting the related photo detecting zone to and from a ground line. The second switch disconnects the related photo detecting zone from the ground line when the first switch connects the related photo detecting zone to the output line. The second switch connects the related photo detecting zone to the ground line when the first switch disconnects the related photo detecting zone from the output line.
    Type: Grant
    Filed: October 27, 2000
    Date of Patent: June 4, 2002
    Assignee: Denso Corporation
    Inventors: Ryoichi Sugawara, Naoki Sano
  • Patent number: 6388387
    Abstract: To provide an optical element in which resistance of electrodes on a scanning side is reduced, a rate of effectively utilizing light generated at organic layers is promoted and shortcircuit between anodes and cathodes is prevented, there is provided an optical element including first electrodes formed on a substrate, organic layers at least including organic light emitting materials formed on the first electrodes and second electrodes formed on the organic layers, in which the first electrodes and the second electrodes are formed to be substantially orthogonal to each other and the organic layers are formed in an island-like shape at positions at which the first electrodes and the second electrodes intersect with each other.
    Type: Grant
    Filed: November 9, 2000
    Date of Patent: May 14, 2002
    Assignee: Sony Corporation
    Inventors: Takashi Hirano, Tatsuya Sasaoka, Mitsunobu Sekiya, Naoki Sano, Tetsuo Nakayama
  • Patent number: 6380673
    Abstract: An organic EL display that realizes low electric power consumption and display with high brightness by decreasing the resistance of the electrode on the scanning side is provided.
    Type: Grant
    Filed: September 16, 1999
    Date of Patent: April 30, 2002
    Assignee: Sony Corporation
    Inventors: Mitsunobu Sekiya, Takashi Hirano, Tetsuo Nakayama, Naoki Sano, Tatsuya Sasaoka
  • Publication number: 20020027414
    Abstract: An organic EL display that realizes low electric power consumption and display with high brightness by decreasing the resistance of the electrode on the scanning side is provided.
    Type: Application
    Filed: September 16, 1999
    Publication date: March 7, 2002
    Inventors: MITSUNOBU SEKIYA, TAKASHI HIRANO, TETSUO NAKAYAMA, NAOKI SANO, TATSUYA SASAOKA
  • Publication number: 20020006248
    Abstract: To provide a small and lightweight optical switching element with a simple structure capable of fast response, and an optical switching apparatus employing the optical switching element. Optical extraction unit contacts an upper substrate with electrostatic attraction generated between a transparent electrode of the optical extraction unit and a transparent electrode of the upper substrate. In the case that light enters one V-shaped trench of the upper substrate vertically, the light enters the optical extraction unit of the upper substrate and is emitted from a back of the optical extraction unit (a tapered unit). Subsequently, the incident light P1 passes through a lower substrate and is converted into transmission light. With electrostatic attraction generated between a transparent electrode of the lower substrate and a transparent electrode of the optical extraction unit, the optical extraction unit is attracted to a lower substrate side.
    Type: Application
    Filed: April 17, 2001
    Publication date: January 17, 2002
    Inventors: Takuya Makino, Kazuhiro Hane, Kazuhito Hori, Masaki Hara, Naoki Sano, Hidenori Watanabe
  • Publication number: 20010022387
    Abstract: A process for pattern forming during semiconductor manufacturing comprises the steps of forming a resist pattern on a substrate, then a metallic layer, of aluminum for example, is applied to the complete surface of the substrate and the resist pattern, by spattering or the like. Next a heating step is carried out. The heating step is accomplished by immersing the resist pattern in a solvent heated in the vicinity of a boiling point thereof, for effecting expansion of the resist pattern. Then the resist pattern is removed along with undesired remnants of the metallic layer which are adhered to the resist pattern.
    Type: Application
    Filed: May 16, 2001
    Publication date: September 20, 2001
    Inventors: Naoki Sano, Toshiyuki Sameshima, Masaki Hara, Setsuo Usui
  • Patent number: 6291366
    Abstract: A target semiconductor device can be obtained stably by reforming an insulating film and a semiconductor. In a process of manufacturing a semiconductor device, at least one of the semiconductor and the insulating film is reformed after an annealing process for annealing the semiconductor at a temperature ranging from 20 to 400° C. in the atmosphere containing a gas of water (H2O) with a partial pressure from 1 Torr to a saturated vapor pressure for an annealing time ranging from 15 seconds to 20 hours.
    Type: Grant
    Filed: August 14, 1995
    Date of Patent: September 18, 2001
    Assignee: Sony Corporation
    Inventors: Naoki Sano, Masaki Hara, Mitsunobu Sekiya, Toshiyuki Sameshima
  • Publication number: 20010019901
    Abstract: A target semiconductor device can be obtained stably by reforming an insulating film and a semiconductor. In a process of manufacturing a semiconductor device, at least one of the semiconductor and the insulating film is reformed after an annealing process for annealing the semiconductor at a temperature ranging from 20 to 400° C. in the atmosphere containing a gas of water (H2O) with a partial pressure from 1 Torr to a saturated vapor pressure for an annealing time ranging from 15 seconds to 20 hours.
    Type: Application
    Filed: February 8, 2001
    Publication date: September 6, 2001
    Inventors: Naoki Sano, Masaki Hara, Mitsunobu Sekiya, Toshiyuki Sameshima
  • Patent number: 6251561
    Abstract: A recording film is formed by a vacuum film formation process. The recording film contains a substance which is thermally decomposed when a recording laser beam is irradiated thereto. When the substance is thermally decomposed by irradiation of the recording laser beam, a substance generated by the thermal decomposition is precipitated within the recording film, and therefore a change in complex index of refraction is caused predominantly over the raising deformation in the recording film. As a result, information is recorded in the recording film while causing almost no raising deformation of the recording film.
    Type: Grant
    Filed: January 22, 1999
    Date of Patent: June 26, 2001
    Assignee: Denso Corporation
    Inventors: Shoichi Kawai, Hironari Kuno, Naoki Sano, Ryoichi Sugawara
  • Patent number: 6215250
    Abstract: To provide an optical element in which resistance of electrodes on a scanning side is reduced, a rate of effectively utilizing light generated at organic layers is promoted and shortcircuit between anodes and cathodes is prevented, there is provided an optical element including first electrodes formed on a substrate, organic layers at least including organic light emitting materials formed on the first electrodes and second electrodes formed on the organic layers, in which the first electrodes and the second electrodes are formed to be substantially orthogonal to each other and the organic layers are formed in an island-like shape at positions at which the first electrodes and the second electrodes intersect with each other.
    Type: Grant
    Filed: August 3, 1999
    Date of Patent: April 10, 2001
    Assignee: Sony Corporation
    Inventors: Takashi Hirano, Tatsuya Sasaoka, Mitsunobu Sekiya, Naoki Sano, Tetsuo Nakayama
  • Patent number: 6120338
    Abstract: The present invention provides a method of manufacturing an organic EL display capable of decreasing the resistance of scanning-side electrodes, and improving the efficiency of utilization of light emitted in organic layers. In the manufacturing method, stripe first electrodes made of a transparent conductive material are formed in parallel on a transparent substrate, and then an insulation layer is formed on the transparent substrate with the apertures formed above the first electrodes. An organic film 24 composed of a film of an organic luminescent material, a second electrode material film and a protecting film is laminated in this order on the transparent substrate to cover the insulation layer, and then independent island resist patterns are formed on the protecting film.
    Type: Grant
    Filed: October 8, 1999
    Date of Patent: September 19, 2000
    Assignee: Sony Corporation
    Inventors: Takashi Hirano, Tatsuya Sasaoka, Mitsunobu Sekiya, Naoki Sano, Tetsuo Nakayama
  • Patent number: 5991533
    Abstract: A verification support system having the following characteristics: (1) Before actually making a CPU mounted circuit, virtually make a CPU mounted circuit model and an ICE model and perform verification of the CPU mounted circuit mode with logic simulation, by using the ICE model; (2) When an error is found in the verification of a program using logic simulation, the execution and verification of the steps up to one step before the error point is omitted and execution and verification are performed immediately from the error point, for the purpose of error correction; (3) A waveform obtained as a result of logic simulation and a partially enlarged waveform thereof are displayed on different display regions; (4) A display region for displaying a waveform obtained as a result of logic simulation every hour and a display region for saving a displayed waveform obtained when logic simulation is stopped, are provided separately; (5) When there are a plurality of target logic models, waveforms of logic simulation re
    Type: Grant
    Filed: October 10, 1997
    Date of Patent: November 23, 1999
    Assignee: Yokogawa Electric Corporation
    Inventors: Naoki Sano, Takeshi Yamamoto, Manabu Noriyasu, Satoru Natsui, Yuji Amano, Atsushi Ogasawara, Yuko Mizuta, Yoko Takihana
  • Patent number: 5910015
    Abstract: The present invention is directed to a thin film transistor (TFT) structure having a channel region formed of a crystallized SiGe and is to provide a thin film transistor having a large carrier mobility. In this case, a channel region (4) is formed of a crystallized SiGe thin film.
    Type: Grant
    Filed: February 18, 1998
    Date of Patent: June 8, 1999
    Assignee: Sony Corporation
    Inventors: Toshiyuki Sameshima, Masaki Hara, Naoki Sano, Dharam Pal Gosain, Setsuo Usui
  • Patent number: 5889292
    Abstract: The present invention is directed to a thin film transistor (TFT) structure having a channel region formed of a crystallized SiGe and is to provide a thin film transistor having a large carrier mobility. In this case, a channel region (4) is formed of a crystallized SiGe thin film.
    Type: Grant
    Filed: December 13, 1995
    Date of Patent: March 30, 1999
    Assignee: Sony Corporation
    Inventors: Toshiyuki Sameshima, Masaki Hara, Naoki Sano, Dharam Pal Gosain, Setsuo Usui
  • Patent number: 5758123
    Abstract: A verification support system wherein before a CPU mounted circuit is actually made such circuit model and an ICE model are made virtually and verification of such circuit model is performed using logic simulation on the ICE model; and when an error is found execution and verification up to the error point are omitted and are performed immediately after the error point to correct the error. A waveform, obtained by logic simulation, and a partially enlarged waveform thereof are displayed on different display regions for each time period and a display region is provided for saving a displayed waveform obtained when logic simulation is stopped. In another aspect of the invention, before an actual system is made by PLC, such PLC model is verified, and a test program is carried out to obtain verification when a process model is detached from the PLC model, and a sequence program is carried out by using a general purpose simulator with a debugging function.
    Type: Grant
    Filed: April 11, 1995
    Date of Patent: May 26, 1998
    Assignee: Yokogawa Electric Corporation
    Inventors: Naoki Sano, Takeshi Yamamoto, Manabu Noriyasu, Satoru Natsui, Yuji Amano, Atsushi Ogasawara, Yuko Mizuta, Yoko Takihana
  • Patent number: 5726487
    Abstract: The present invention is directed to a thin film transistor (TFT) structure having a channel region formed of a crystallized SiGe and is to provide a thin film transistor having a large carrier mobility. In this case, a channel region (4) is formed of a crystallized SiGe thin film.
    Type: Grant
    Filed: October 28, 1994
    Date of Patent: March 10, 1998
    Assignee: Sony Corporation
    Inventors: Toshiyuki Sameshima, Masaki Hara, Naoki Sano, Dharam Pal Gosain, Setsuo Usui
  • Patent number: 5648276
    Abstract: A method and an apparatus for fabricating a thin film semiconductor device are disclosed. An a-Si:H thin film produced on a wafer is melting-recrystallized by irradiating a laser beam to it in a laser annealing chamber to produce a polycrystalline Si thin film. The wafer is then transported to a CVD chamber without exposing it to the outside air. A gate insulating film is produced on a clean surface of the polycrystalline Si thin film in the CVD chamber. In another case, an a-Si:H thin film is melting-recrystallized in the laser annealing chamber to produce a polycrystalline Si thin film and then the wafer is transported to a hydrogenating chamber without exposing it to the outside air. Thereafter the polycrystalline Si thin film is plasma hydrogenated in the hydrogenating chamber.
    Type: Grant
    Filed: May 26, 1994
    Date of Patent: July 15, 1997
    Assignee: Sony Corporation
    Inventors: Masaki Hara, Naoki Sano, Toshiyuki Sameshima, Atsushi Kohno, Mitsunobu Sekiya, Yasuhiro Kanaya, Michihisa Yano
  • Patent number: 5591653
    Abstract: The present invention is directed to a thin film transistor (TFT) structure having a channel region formed of a crystallized SiGe and is to provide a thin film transistor having a large carrier mobility. In this case, a channel region (4) is formed of a crystallized SiGe thin film.
    Type: Grant
    Filed: May 15, 1995
    Date of Patent: January 7, 1997
    Assignee: Sony Corporation
    Inventors: Toshiyuki Sameshima, Masaki Hara, Naoki Sano, Dharam Pal Gosain, Setsuo Usui