Patents by Inventor Naoki Tanahashi
Naoki Tanahashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7331695Abstract: A visible light-reflecting member is disclosed which uses a plate or a film for reflecting visible lights, whose reflective surface is provided with an aluminum thin film having an aluminum purity of not less than 99 mass % and an X-ray diffraction pattern wherein, among peak intensities ascribed to aluminum, the peak intensity ascribed to the (111) plane is higher than the total of the other peak intensities.Type: GrantFiled: February 27, 2004Date of Patent: February 19, 2008Assignee: Foundation for Advancement of International ScienceInventors: Tadahiro Ohmi, Akihiro Morimoto, Naoki Tanahashi
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Publication number: 20080037124Abstract: An optical member utilizing diffraction, which comprises a substrate having a fine structure comprising microstructures with an interval of 50-1,000 nm between the adjacent microstructures on a substrate surface, wherein the substrate has a surface layer portion comprising a region containing fluorine atoms in an amount larger than that in the inner layer portion thereof. The microstructures are preferably micro-protrusions each tapering toward the tip in the direction perpendicular to the substrate surface. The optical member is manufactured by a method comprising a step of exposing the surface of the substrate having a fine structure comprising microstructures with an interval of 50-1,000 nm between the adjacent microstructures to an atmosphere containing a fluorine gas.Type: ApplicationFiled: March 31, 2005Publication date: February 14, 2008Applicants: ZEON CORPORATIONInventors: Tadahiro Ohmi, Naoki Tanahashi, Masahiko Hayashi
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Publication number: 20070046379Abstract: A cascode connection circuit includes a first field effect transistor (FET) which has a source terminal and a drain terminal, the source terminal being connected to ground; a second FET which has a source terminal and a gate terminal, the source terminal being connected to the drain terminal of the first FET; and a first resistor and a first capacitor connected in series between the source terminal of the first FET and the gate terminal of the second FET. The first FET and the second FET are cascode-connected to each other. The product of the resistance of the first resistor and the capacitance of the first capacitor does not exceed 0.1 times the period of an operating frequency of the circuit.Type: ApplicationFiled: May 22, 2006Publication date: March 1, 2007Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Naoki Tanahashi, Akira Inoue
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Publication number: 20060215409Abstract: A visible light-reflecting member is disclosed which uses a plate or a film for reflecting visible lights, whose reflective surface is provided with an aluminum thin film having an aluminum purity of not less than 99 mass % and an X-ray diffraction pattern wherein, among peak intensities ascribed to aluminum, the peak intensity ascribed to the (111) plane is higher than the total of the other peak intensities.Type: ApplicationFiled: February 27, 2004Publication date: September 28, 2006Inventors: Tadahiro Ohmi, Akihiro Morimoto, Naoki Tanahashi
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Publication number: 20060193940Abstract: A member for a resin molding machine wherein it has a face contacting with a molten resin, and at least a part of the face is covered with a film of an oxide of a base material of the face or a component contained in the base material. The use of the member in the molding of a resin allows the prevention of the incorporation of a contaminant associated with the deterioration of a melt of the resin into a molded article from the resin.Type: ApplicationFiled: February 26, 2004Publication date: August 31, 2006Inventors: Tadahiro Ohmi, Masafumi Kitano, Naoki Tanahashi
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Publication number: 20060081842Abstract: A plurality of diffused resistors and a plurality of wirings (resistive elements) are alternately disposed along a virtual line, and those diffused resistors and wirings are connected in series by contact vias. In the same wiring layer as that of the wirings, a dummy pattern is formed so as to surround a formation region of the wirings and the diffused resistors. A space between the dummy pattern and the wirings is set in accordance with, for example, a minimum space between wirings in a chip formation portion.Type: ApplicationFiled: November 15, 2005Publication date: April 20, 2006Applicant: FUJITSU LIMITEDInventors: Sachie Tone, Hiroyuki Uno, Naoki Tanahashi, Naoki Nishida
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Patent number: 6992327Abstract: A plurality of diffused resistors and a plurality of wirings (resistive elements) are alternately disposed along a virtual line, and those diffused resistors and wirings are connected in series by contact vias. In the same wiring layer as that of the wirings, a dummy pattern is formed so as to surround a formation region of the wirings and the diffused resistors. A space between the dummy pattern and the wirings is set in accordance with, for example, a minimum space between wirings in a chip formation portion.Type: GrantFiled: May 30, 2003Date of Patent: January 31, 2006Assignee: Fujitsu LimitedInventors: Sachie Tone, Hiroyuki Uno, Naoki Tanahashi, Naoki Nishida
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Publication number: 20030222260Abstract: A plurality of diffused resistors and a plurality of wirings (resistive elements) are alternately disposed along a virtual line, and those diffused resistors and wirings are connected in series by contact vias. In the same wiring layer as that of the wirings, a dummy pattern is formed so as to surround a formation region of the wirings and the diffused resistors. A space between the dummy pattern and the wirings is set in accordance with, for example, a minimum space between wirings in a chip formation portion.Type: ApplicationFiled: May 30, 2003Publication date: December 4, 2003Applicant: FUJITSU LIMITEDInventors: Sachie Tone, Hiroyuki Uno, Naoki Tanahashi, Naoki Nishida
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Patent number: 6525144Abstract: A norbornene polymer comprising a repeating unit derived from a norbornene monomer having a cyclic hydrocarbon structure (I) derived from the norbornene ring which constitutes at least a part of the main chain, another cyclic hydrocarbon structure (II), which shares one carbon-carbon bond with the cyclic hydrocarbon structure (I) and has 4 to 6 carbon atoms, and a monocyclic or polycyclic hydrocarbon structure (III), which shares one carbon-carbon bond with the cyclic hydrocarbon structure (II), in a proportion of 20 to 100 mol % based on the whole repeating unit of the polymer, wherein the number average molecular weight is within a range of 1,000 to 1,000,000, and a peak area (A) on a high magnetic field side and a peak area (B) on a low magnetic field side in methylene peaks derived from the methylene groups in the cyclic hydrocarbon structure (III) in a 13C-NMR spectrum as determined in heavy chloroform (TMS standard) satisfy a relationship of the expression: B/(A+B)≦0.Type: GrantFiled: May 5, 2000Date of Patent: February 25, 2003Assignee: Nippon Zeon Co., Ltd.Inventors: Naoki Tanahashi, Hidehiro Ito, Toshihide Murakami
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Publication number: 20020014929Abstract: A microwave/millimeter-wave integrated circuit realizes stable oscillation by reducing time-base variation in load impedance. This IC connects an oscillator to the input terminal of a lange coupler, and connects to the isolation port of the lange coupler a terminating resistor with resistance equal to the load impedance connected to the output terminals of the lange coupler. This stabilizes load impedance to the oscillator, and reduces variation in the oscillation frequency as a result of changes in load impedance.Type: ApplicationFiled: September 20, 2001Publication date: February 7, 2002Inventors: Takuo Kashiwa, Yoshinobu Sasaki, Naoki Tanahashi
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Patent number: 6300840Abstract: A microwave/millimeter-wave integrated circuit (IC) realizes stable oscillation by reducing time-based variation of a load impedance. This IC connects an oscillator to an input terminal of a Lange coupler and connects to the isolation port of the Lange coupler a terminating resistor having a resistance equal to the load impedance connected to the output terminals of the Lange coupler. This connection stabilizes load impedance to the oscillator, and reduces variation in the oscillation frequency as a result of changes in load impedance.Type: GrantFiled: December 9, 1999Date of Patent: October 9, 2001Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Takuo Kashiwa, Yoshinobu Sasaki, Naoki Tanahashi
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Patent number: 6043308Abstract: Conductive rubber compositions comprising a vulcanizate of a rubber component (A), a rubber component (B) vulcanized by a mechanism different from that in the rubber component (A), and conductive particles, a production process thereof, conductive rubber members making use of such a conductive rubber composition, a production process of the conductive rubber members, conductive rubber-covered rolls, and image forming apparatus equipped with the conductive rubber-covered roll are provided.Type: GrantFiled: May 11, 1998Date of Patent: March 28, 2000Assignee: Nippon Zeon Co., Ltd.Inventors: Naoki Tanahashi, Kouichirou Maeda
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Patent number: 5854799Abstract: A video decoding apparatus for decoding encoded video data to continuously produce decoded pictures. The video data includes a series of pictures, each picture contains a series of slices, and each slice contains a series of macroblocks. A dequantizer performs dequantization of the video data based upon a quantization threshold value. A motion-vector restoring circuit restores data for each macroblock. A direct current error detector is provided to detect erroneous macroblocks based upon the dequantized data. A motion-area error detector is provided to detect erroneous macroblocks based upon the restored motion vector data. An erroneous macroblock is replaced by a corresponding macroblock from a preceding picture. Subsequent macroblocks in a slice may also be replaced by corresponding macroblocks from a preceding picture.Type: GrantFiled: November 29, 1995Date of Patent: December 29, 1998Assignee: Sanyo Electric Co., Ltd.Inventors: Shigeyuki Okada, Naoki Tanahashi, Hayato Nakashima
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Patent number: 5754241Abstract: An MPEG video decoder capable of preventing a buffer for storing a video stream from overflowing and/or underflowing. The video decoding apparatus decodes a coded video bit stream including a series of pictures to produce decoded pictures. The video decoding apparatus includes: a bit buffer for temporarily storing the video bit stream, a decoding circuit for receiving the video bit stream output from the bit buffer and decoding the video bit stream to produce decoded pictures, and a video bit stream control circuit for controlling an amount of the video bit stream to be supplied to the decoding circuit from the bit buffer based on an amount of data of the video bit stream stored in the bit buffer.Type: GrantFiled: November 14, 1995Date of Patent: May 19, 1998Assignee: Sanyo Electric Co., LtdInventors: Shigeyuki Okada, Keita Kawahara, Naoki Tanahashi, Hayato Nakashima
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Patent number: 5748514Abstract: Discrete cosine transform circuits suitable for inverse discrete cosine transform (IDCT) or forward discrete cosine transform (FDCT) are disclosed. An IDCT circuit includes a group of multipliers and a group of adders/subtracters. The multipliers receive plural pieces of input data which are externally supplied in parallel. Each multiplier has a cosine constant to multiply to the received input data. The adders/subtracters receive multiplication results from the multipliers and perform addition/subtraction thereon to produce output data, which is the result of inverse discrete cosine transform of the input data. An FDCT circuit includes a group of input-stage adders/subtracters, a group of multipliers, and a group of output-stage adders. The input-stage adders/subtracters perform addition/subtraction on input data which are externally supplied in parallel. Computation results of the input-stage adders/subtracters is supplied to the multipliers.Type: GrantFiled: November 29, 1995Date of Patent: May 5, 1998Assignee: Sanyo Electric Co., Ltd.Inventors: Shigeyuki Okada, Naoki Tanahashi, Hayato Nakashima