Patents by Inventor Naoki Yokoi

Naoki Yokoi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220246484
    Abstract: Disclosed herein is a method that includes forming a contact plug to be embedded in a first insulating film formed on a semiconductor substrate; forming a probe pad on the first insulating film to contact with the contact plug; performing a test operation by probing the probe pad; removing the probe pad; forming a second insulating film to cover the contact plug after removing the probe pad; and forming a pad electrode to be embedded in the second insulating film.
    Type: Application
    Filed: February 2, 2021
    Publication date: August 4, 2022
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: Naoki Yokoi
  • Patent number: 11381331
    Abstract: A first prediction unit 83 predicts the amount of future communication quality deterioration or the presence or absence of occurrence of future communication quality deterioration in a communication section between one communication device and another communication device communicably connected to the one communication device by using a first learning model generated on the basis of first attributes being attributes related to a cause of communication quality deterioration in the communication section. A second prediction unit 84 predicts the amount of future communication quality deterioration or the presence or absence of occurrence of future communication quality deterioration outside the communication section regarding one communication device by using a second learning model generated on the basis of second attributes being attributes related to a cause of communication quality deterioration outside the communication section regarding the one communication device.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: July 5, 2022
    Assignee: NEC CORPORATION
    Inventors: Ichirou Akimoto, Daisuke Yokoi, Naoki Sawada, Masayuki Ikeda
  • Publication number: 20220203668
    Abstract: The supply unit is used in a printing device including a printing head configured to perform printing process of a viscous fluid on a printing target using a screen mask, a collection section having a collection member configured to contact the screen mask to collect and move the viscous fluid and a collecting and moving section configured to move the collection member in a predetermined printing direction. The supply unit includes a supply section having a mounting section capable of mounting and dismounting a cartridge accommodating the viscous fluid, a driving section configured to move the supply section in the supply operation direction, a detection member, and a supply section detecting section configured to detect whether the supply section is positioned in a passage space where the collection section and the supply section do not contact each other by the position of the detection member.
    Type: Application
    Filed: April 26, 2019
    Publication date: June 30, 2022
    Applicant: FUJI CORPORATION
    Inventors: Yoshimune YOKOI, Naoki MATSUZAKI
  • Patent number: 8258630
    Abstract: A semiconductor device includes: a first layer; a second layer above the first layer; first and second multi-layered structures; and a supporter. The first and second multi-layered structures extend from the first layer to connect to the second layer. The supporter extends from the first layer to connect to the second layer. The supporter is between the first and second multi-layered structures. The supporter is separated from the first and second multi-layered structures by empty space.
    Type: Grant
    Filed: October 26, 2009
    Date of Patent: September 4, 2012
    Assignee: Elpida Memory, Inc.
    Inventor: Naoki Yokoi
  • Patent number: 7919803
    Abstract: A semiconductor memory device in which a plurality of capacitors each including a columnar lower electrode, a capacitor insulation film and an upper electrode are stacked with interlayer films therebetween, a contact plug connects an upper face of each lower electrode of a lower layer with a bottom face of each lower electrode of an upper layer, and another contact plug connects upper electrodes of the capacitors in respective layers with each other.
    Type: Grant
    Filed: September 19, 2008
    Date of Patent: April 5, 2011
    Assignee: Elpida Memory, Inc.
    Inventor: Naoki Yokoi
  • Publication number: 20100102455
    Abstract: A semiconductor device includes: a first layer; a second layer above the first layer; first and second multi-layered structures; and a supporter. The first and second multi-layered structures extend from the first layer to connect to the second layer. The supporter extends from the first layer to connect to the second layer. The supporter is between the first and second multi-layered structures. The supporter is separated from the first and second multi-layered structures by empty space.
    Type: Application
    Filed: October 26, 2009
    Publication date: April 29, 2010
    Applicant: ELPIDA MEMORY, INC
    Inventor: Naoki YOKOI
  • Publication number: 20090088909
    Abstract: In a batch cleaning apparatus having a one-bath-type cleaning tank, control is performed such that an average temperature of cleaning liquid in the cleaning tank is uniform among different batches. The one-bath-type cleaning tank has a megasonic oscillator for cleaning objects to be cleaned. A control computer controls the supply temperature of pure water supplied from a pure water heating device to dilute chemical solution so that variation in solution temperature occurring during application of megasonic waves is compensated. The objects to be cleaned are cleaned with an average solution temperature kept at a fixed level for all the batches, while maintaining a high cleaning efficiency.
    Type: Application
    Filed: September 25, 2008
    Publication date: April 2, 2009
    Applicant: ELPIDA MEMORY, INC.
    Inventor: Naoki Yokoi
  • Publication number: 20090078981
    Abstract: A semiconductor memory device in which a plurality of capacitors each including a columnar lower electrode, a capacitor insulation film and an upper electrode are stacked with interlayer films therebetween, a contact plug connects an upper face of each lower electrode of a lower layer with a bottom face of each lower electrode of an upper layer, and another contact plug connects upper electrodes of the capacitors in respective layers with each other.
    Type: Application
    Filed: September 19, 2008
    Publication date: March 26, 2009
    Applicant: Elpida Memory, Inc.
    Inventor: Naoki YOKOI
  • Patent number: 7494864
    Abstract: A method for production of a semiconductor device including the steps of: forming a gate insulating film, a polysilicon film and a first insulating film on a silicon substrate; patterning the first insulating film; forming a metal film; forming a silicide layer by reacting the polysilicon film with the metal film; forming a second insulating film after removing an unreacted metal film; removing the second insulating film such that the first insulating film is exposed and the second insulating film remains on a region which is not covered with the first insulating film; forming a gate electrode having a silicide layer on the upper layer side and a polysilicon layer on the lower layer side by carrying out etching using the second insulating film as a mask after removing the first insulating film; forming a third insulating film on the side surface of the gate electrode; and forming an interlayer insulating film and forming a contact hole therein.
    Type: Grant
    Filed: November 3, 2006
    Date of Patent: February 24, 2009
    Assignee: Elpida Memory, Inc.
    Inventor: Naoki Yokoi
  • Patent number: 7332395
    Abstract: A method of manufacturing a stack capacitance type capacitor is provided, which prevents the problem that the capacitor cannot be formed because a lower electrode collapses with the external wall thereof exposed in forming the lower electrode of the capacitor in a deep hole formed in silicon oxide, and removing silicon oxide that is a support base material for the lower electrode using a solution containing hydrogen fluoride to expose the external wall of the lower electrode. According to the invention, the support base material in which a deep hole is formed is formed with an amorphous carbon film, the amorphous carbon film used as the support base material for the lower electrode is removed by dry etching after forming the lower electrode, and it is thereby possible to prevent the lower electrode from collapsing.
    Type: Grant
    Filed: October 24, 2005
    Date of Patent: February 19, 2008
    Assignee: Elpida Memory Inc.
    Inventor: Naoki Yokoi
  • Publication number: 20070202649
    Abstract: In order to produce a MOS transistor having a gate electrode on a slope, patterning is first performed for a lower-layer gate electrode film near a lower end of the slope. A space between the lower-layer gate electrode films is filled with a filler so that the filler has the same height as a primary surface of a substrate. After an upper-layer gate electrode film is deposited, patterning is performed for the gate electrode films.
    Type: Application
    Filed: February 13, 2007
    Publication date: August 30, 2007
    Applicant: ELPIDA MEMORY, INC.
    Inventor: Naoki Yokoi
  • Publication number: 20070158723
    Abstract: A semiconductor storage device of the present invention has a configuration in which a plurality of memory cells respectively including a transistor connected to a storage element for accumulating data are used, a bit line and a word line for specifying one of a plurality of memory cells are used. A structure in which a source electrode and a drain electrode hold an active region is formed vertically to a substrate face. The same bit line is connected to the first two-memory cell unit adjacently formed in a predetermined direction. The same word line is formed, which is a gate electrode of the transistors of the second two-memory cell unit which includes one memory cell of the first two-memory cell unit and which is adjacently formed in the predetermined direction.
    Type: Application
    Filed: January 5, 2007
    Publication date: July 12, 2007
    Applicant: ELPIDA MEMORY, INC.
    Inventor: Naoki YOKOI
  • Publication number: 20070131358
    Abstract: A shutter curtain lifting prevention structure comprises a shutter curtain formed by connecting a plurality of slats via an interlock portion in the vertical direction, guide rails standing on both sides of an opening of the construction, and a cutout recess being integrally formed at the guide groove of each guide rail. The cutout recess is formed by horizontally cutting out the interior side plane portion of the front face located above and in the vicinity of the floor surface, such that when a bottom plate of the shutter curtain kept in a shut state is lifted, a connection portion of the bottom plate and the slat, which is opposed to the cutout recess is made engaged by the engaging portion defined by the cutout recess, thus preventing lifting of the shutter curtain.
    Type: Application
    Filed: September 28, 2004
    Publication date: June 14, 2007
    Inventors: Shinya Iwasaki, Naoki Yokoi, Takanobu Kuribayashi, Mitsuhiro Yoshida
  • Publication number: 20070105296
    Abstract: A method for production of a semiconductor device including the steps of: forming a gate insulating film, a polysilicon film and a first insulating film on a silicon substrate; patterning the first insulating film; forming a metal film; formin a silicide layer by reacting the polysilicon film with the metal film; forming a second insulating film after removing an unreacted metal film; removing the second insulating film such that the first insulating film is exposed and the second insulating film remains on a region which is not covered with the first insulating film; forming a gate electrode having a silicide layer on the upper layer side and a polysilicon layer on the lower layer side by carrying out etching using the second insulating film as a mask after removing the first insulating film; forming a third insulating film on the side surface of the gate electrode; and forming an interlayer insulating film and forming a contact hole therein.
    Type: Application
    Filed: November 3, 2006
    Publication date: May 10, 2007
    Inventor: Naoki YOKOI
  • Publication number: 20060099768
    Abstract: A method of manufacturing a stack capacitance type capacitor is provided, which prevents the problem that the capacitor cannot be formed because a lower electrode collapses with the external wall thereof exposed in forming the lower electrode of the capacitor in a deep hole formed in silicon oxide, and removing silicon oxide that is a support base material for the lower electrode using a solution containing hydrogen fluoride to expose the external wall of the lower electrode. According to the invention, the support base material in which a deep hole is formed is formed with an amorphous carbon film, the amorphous carbon film used as the support base material for the lower electrode is removed by dry etching after forming the lower electrode, and it is thereby possible to prevent the lower electrode from collapsing.
    Type: Application
    Filed: October 24, 2005
    Publication date: May 11, 2006
    Inventor: Naoki Yokoi
  • Publication number: 20050024812
    Abstract: After a conductive film serving as a capacitor lower electrode is formed, the subsequent process steps are performed with the capacitor lower electrode always supported by an interlayer insulating film, a conductive film serving as a portion of a capacitor upper electrode, and a capacitor dielectric film. Therefore, complete exposure of the conductive film serving as the capacitor lower electrode does not take place during a manufacturing process of a semiconductor device. Consequently, a disadvantage that the conductive film serving as the capacitor lower electrode is bent can be avoided. A method of manufacturing a semiconductor device achieving improvement in a yield thereof and a semiconductor device manufactured with such a manufacturing method can thus be obtained.
    Type: Application
    Filed: May 26, 2004
    Publication date: February 3, 2005
    Inventor: Naoki Yokoi
  • Patent number: 6837963
    Abstract: A semiconductor device producing method that can clean an edge part of a semiconductor substrate with certainty is provided. The method of producing a semiconductor device includes a step of generating ions and a step of accelerating the ions by means of an electric field and radiating an ion flow onto an edge part of a semiconductor substrate to clean the edge part of the semiconductor substrate. The semiconductor substrate is moved relative to the ion flow while maintaining a state in which the ion flow is being radiated onto the edge part. The step of generating ions includes applying a high-frequency voltage between a pair of electrodes to generate the ions between the electrodes.
    Type: Grant
    Filed: October 22, 2001
    Date of Patent: January 4, 2005
    Assignees: Renesas Technology Corp., Matsushita Electric Industrial Co., Ltd.
    Inventors: Hiroshi Tanaka, Naoki Yokoi, Yasuhiro Asaoka, Seiji Muranaka, Toshihiko Nagai
  • Patent number: 6730239
    Abstract: A cleaning agent for a semiconductor device contains a hydroxide, water and a compound expressed in the following general formula (I) and/or the following general formula (II): HO—((EO)x—(PO)y)z—H  (I) R—[(EO)x—(PO)y)z—H]m  (II) Thus provided is a cleaning agent for a semiconductor device, which is so improved as not to disconnect a wire or an embedded conductive layer.
    Type: Grant
    Filed: October 4, 2000
    Date of Patent: May 4, 2004
    Assignees: Renesas Technology Corp., Sumitomo Chemical Company, Limited
    Inventors: Itaru Kanno, Naoki Yokoi, Hiroshi Morita, Naoki Ichiki, Hideaki Nezu, Masayuki Takashima
  • Publication number: 20040016447
    Abstract: The present invention provides a cleaning equipment provided with a cleaning solution tank, a cleaning solution supply route for supplying the cleaning solution stored in the cleaning solution tank to a cleaning bath, a cleaning solution return route for returning the cleaning solution that has been supplied to the cleaning bath to the cleaning solution tank, a gas supply route for supplying a purge gas into the cleaning solution tank, and a gas discharge route for discharging the purge gas from the cleaning solution tank. Moreover, a cleaning solution discharge opening of the cleaning solution return route is immersed in the cleaning solution stored in the cleaning solution tank.
    Type: Application
    Filed: January 27, 2003
    Publication date: January 29, 2004
    Applicants: Matsushita Electrical Industrial Co., Ltd., Mitsubishi Denki Kabushiki Kaisha
    Inventors: Toshihiko Nagai, Itaru Kanno, Naoki Yokoi, Yasuhiro Asaoka, Masahiko Higashi
  • Publication number: 20040011388
    Abstract: A side edge of a wafer is retained by a plurality of chuck pins. A heating-and-cooling section is arranged such that a clearance is defined between a surface of the heating-and-cooling section and a surface of the wafer. The heating-and-cooling section is for heating or cooling the surface thereof. The clearance is filled with liquid by means of a liquid filling section. The surface of the wafer is heated or cooled by way of the thus-filled liquid.
    Type: Application
    Filed: December 31, 2002
    Publication date: January 22, 2004
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hiroshi Tanaka, Naoki Yokoi, Kazutoshi Anabuki, Masahiko Higashi