Patents by Inventor Naoki Yokoyama

Naoki Yokoyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20020018455
    Abstract: There is disclosed a wireless access system in which subscriber registration, deletion, and the like are set in a pertinent wireless base station in accordance with a request from a management center, and remote maintenance is realized. The management center is provided with an SNMP manager, each wireless base station is provided with an SNMP agent, and an SNMP protocol is used to set information of subscriber new registration, registration deletion, operation stop, and operation restart in a subscriber management information table for use in communication permission in accordance with SET request in the wireless access system.
    Type: Application
    Filed: December 11, 2000
    Publication date: February 14, 2002
    Inventor: Naoki Yokoyama
  • Patent number: 5938858
    Abstract: A cleaning method for a video tape recorder (VTR) employs a cleaning liquid. The cleaning liquid is applied to a tape surface of a tape-shaped support. The tape surface then slides against a surface of a VTR component, such as a magnetic head surface, to clean the surface. The cleaning liquid is a mixture of perfluorocarbons having a boiling point of about 56.degree. C. to about 155.degree. C. The cleaning liquid may also contain a hydrocarbon based solvent and a fluorine based resin. The cleaning liquid acts to clean and to prevent redeposition of contaminants on the surface of VTR component.
    Type: Grant
    Filed: February 11, 1998
    Date of Patent: August 17, 1999
    Assignees: Sony Corporation, Taiseishokai Co. Ltd.
    Inventors: Naoki Yokoyama, Taiichiro Yoshimoto
  • Patent number: 5889296
    Abstract: A photodetection device includes a collector layer, a collector electrode connected electrically to the collector layer, a base layer free from a junction region for contacting with an electrode, an emitter layer including at least two, mutually separated emitter regions; and at least two emitter electrodes provided respectively on the emitter regions, wherein the base layer is exposed optically to an external optical radiation.
    Type: Grant
    Filed: May 30, 1997
    Date of Patent: March 30, 1999
    Assignee: Fujitsu Limited
    Inventors: Kenichi Imamura, Naoki Yokoyama
  • Patent number: 5809231
    Abstract: An image transmission system and method for transmitting an image, which has been divided into a plurality of pixel blocks, comprising a transmitting device and a receiving device. The transmitting device includes an information source encoder for dividing an image to be transmitted into a plurality of pixel blocks in an original arrangement, a pixel block dispersing unit for arranging the pixel blocks of the image according to predetermined rules, and a modulator for successively modulating and transmitting the rearranged blocks.
    Type: Grant
    Filed: March 18, 1996
    Date of Patent: September 15, 1998
    Assignee: Kokusai Electric Co., Ltd.
    Inventors: Naoki Yokoyama, Ouichi Oyamada
  • Patent number: 5677551
    Abstract: A photodetection device includes a collector layer, a collector electrode connected electrically to the collector layer, a base layer free from a junction region for contacting with an electrode, an emitter layer including at least two, mutually separated emitter regions; and at least two emitter electrodes provided respectively on the emitter regions, wherein the base layer is exposed optically to an external optical radiation.
    Type: Grant
    Filed: August 17, 1995
    Date of Patent: October 14, 1997
    Assignee: Fujitsu Limited
    Inventors: Kenichi Imamura, Naoki Yokoyama
  • Patent number: 5536967
    Abstract: A Schottky gate electrode of a refractory metal silicide is formed on a compound semiconductor, by which the barrier height is maintained satisfactorily even after heat treatment above 800.degree. C. Accordingly, it is possible to form an impurity diffused region using the Schottky gate electrode as a mask and then to effect the recrystallization of the semiconductor or the activation of the impurity by heat treatment, so that source and drain regions can be positioned by self-alignment relative to the gate electrode.
    Type: Grant
    Filed: October 7, 1994
    Date of Patent: July 16, 1996
    Assignee: Fujitsu Limited
    Inventor: Naoki Yokoyama
  • Patent number: 5389804
    Abstract: A resonant-tunneling heterojunction bipolar transistor (RHBT) device having a superlattice structure and a PN junction. The RHBT includes an emitter layer; a base layer; a collector layer operatively facing the base layer to form a PN junction at the face between the base layer and the collector layer; and a superlattice structure including at least one quantum well defining a sub-band of energy at which carriers resonant-tunnel therethrough, formed at least in the emitter layer and operatively facing to the base layer.The RHBT has a differential negative resistance characteristics for realizing a variety of logic circuits and includes an electron resonance and a positive hole resonance, for which the generation condition is changeable in response to a mole fraction of material of the emitter layer.
    Type: Grant
    Filed: November 8, 1993
    Date of Patent: February 14, 1995
    Assignee: Fujitsu Limited
    Inventors: Naoki Yokoyama, Kenichi Imamura
  • Patent number: 5311465
    Abstract: A semiconductor memory device comprises a memory cell transistor that includes two active parts each including therein an emitter and a base and showing a negative differential resistance. The collector layer is shared commonly by the two active parts and is connected to a bit line, while the emitters forming the two active parts are connected to respective word lines that form a word line pair. The bit line and the word lines forming the word line pair are biased to realize a bistable operational state in the memory cell transistor to hold the information.
    Type: Grant
    Filed: February 22, 1993
    Date of Patent: May 10, 1994
    Assignee: Fujitsu Limited
    Inventors: Toshihiko Mori, Naoki Yokoyama
  • Patent number: 5214297
    Abstract: A high-speed semiconductor device comprising emitter potential barrier layer disposed between an emitter layer and a base layer, a collector layer, and a collector potential barrier layer disposed between the base layer and the collector layer. The collector potential barrier layer has a structure having a barrier height changing from a high level to a low level along the direction from the base layer to the collector layer, whereby, even when no bias voltage is applied between the collector layer and the emitter layer, a collector current can flow through the device.
    Type: Grant
    Filed: July 28, 1992
    Date of Patent: May 25, 1993
    Assignee: Fujitsu Limited
    Inventors: Kenichi Imamura, Naoki Yokoyama, Toshio Ohshima
  • Patent number: 5200349
    Abstract: A Schottky gate electrode of a refractory metal silicide is formed on a compound semiconductor, by which the barrier height is maintained satisfactorily even after heat treatment above 800.degree. C. Accordingly, it is possible to form an impurity diffused region using the Schottky gate electrode as a mask and then to effect the recrystallization of the semiconductor or the activation of the impurity by heat treatment, so that source and drain regions can be positioned by self-alignment relative to the gate electrode.
    Type: Grant
    Filed: July 25, 1988
    Date of Patent: April 6, 1993
    Assignee: Fujitsu Limited
    Inventor: Naoki Yokoyama
  • Patent number: 5173548
    Abstract: Epoxy-modified hydrocarbon resins of this invention are prepared by copolymerizing hydrocarbon olefins mainly consisting of aromatic olefins such as indene, styrene, and coumarone with phenols and epoxidizing the copolymers with epichlorohydrin and are useful as modifiers and base polymers for coatings, adhesives, rubbers, and IC encapsulants and also as raw materials for the compatibilizers for incompatible polymer systems because of their capability of undergoing crosslinking or grafting reactions with polymers having functional groups or chemical compositions reactive with the epoxy groups.
    Type: Grant
    Filed: August 7, 1989
    Date of Patent: December 22, 1992
    Assignee: Nippon Steel Chemical Co., Ltd.
    Inventor: Naoki Yokoyama
  • Patent number: 5151618
    Abstract: A resonant-tunneling heterojunction bipolar transistor (RHBT) device having a superlattice structure and a PN junction. The RHBT includes an emitter layer; a base layer; a collector layer operatively facing the base layer to form a PN junction at the face between the base layer and the collector layer; and a superlattice structure including at least one quantum well defining a sub-band of energy at which carriers resonant-tunnel therethrough, formed at least in the emitter layer and operatively facing to the base layer. The RHBT has a differential negative resistance characteristics for realizing a variety of logic circuits and includes an electron resonance and a positive hole resonance, for which the generation condition is changeable in response to a mole fraction of material of the emitter layer.
    Type: Grant
    Filed: February 22, 1991
    Date of Patent: September 29, 1992
    Assignee: Fujitsu Limited
    Inventors: Naoki Yokoyama, Kenichi Imamura
  • Patent number: 5130766
    Abstract: A quantum interference type semiconductor device is composed of at least one bifurcated branch conductive channel with a heterojunction in a semiconductor with a band discontinuity that produced a potential well between two semiconductor regions into which a carrier is injected and from which a carrier is drained, at least one gate electrode is arranged at the side of the one bifurcated branch conduction channel, and a kind of filter using a resonance tunneling barrier arranged before or upstream of the semiconductor region into which a carrier is injected. The filter passes a carrier having a certain energy legvel to the channel whereby the level of the carrier traveling in the channel becomes equal to realize a good quantum interference effect.
    Type: Grant
    Filed: August 3, 1989
    Date of Patent: July 14, 1992
    Assignee: Fujitsu Limited
    Inventors: Hiroshi Arimoto, Shunichi Muto, Shigehiko Sasa, Makoto Okada, Naoki Yokoyama
  • Patent number: 5031005
    Abstract: A semiconductor device comprises stacked first through fifth semiconductor layers. The semiconductor device has an energy level condition of .vertline.Ec.sub.3 -Ec.sub.1 .vertline..apprxeq..vertline.Ev.sub.3 -Ev.sub.5 .vertline., where Ec.sub.3 is a resonant energy level of electrons in a conduction band of the third layer and Ev.sub.3 is a resonant energy level of holes in a valence band thereof, and Ec.sub.1 is an energy level of a conduction band of the first layer and Ev.sub.5 is an energy level of a valence band of the fifth layer.
    Type: Grant
    Filed: October 21, 1987
    Date of Patent: July 9, 1991
    Assignee: Fujitsu Limited
    Inventors: Toshiro Futatsugi, Naoki Yokoyama, Kenichi Imamura
  • Patent number: 5027179
    Abstract: A resonant-tunneling heterojunction bipolar transistor (RHBT) device having a superlattice structure and a PN junction. The RHBT includes an emitter layer, a base layer, a collector layer facing the base layer to form a PN junction at the interface between the base layer and the collector layer, and a superlattice structure including at least one quantum well defining a sub-band of energy at which carriers resonant-tunnel therethrough. The superlattice is formed at least in the emitter layer and faces. The RHBT has a differential negative resistance characteristic for realizing a variety of logic circuits and includes an electron resonance and a positive hole resonance, for which the generation condition is changeable in response to a mole fraction of material of the emitter layer.
    Type: Grant
    Filed: October 22, 1990
    Date of Patent: June 25, 1991
    Assignee: Fujitsu Limited
    Inventors: Naoki Yokoyama, Kenichi Imamura
  • Patent number: 5021863
    Abstract: A semiconductor quantum effect device having negative differential resistance characteristics includes a composite potential barrier layer including a first potential barrier layer and a second potential barrier layer; a carrier injection side semiconductor layer connected in contact with the first potential barrier layer; and a carrier injected side semiconductor layer connected in contact with the second potential barrier layer.
    Type: Grant
    Filed: September 12, 1989
    Date of Patent: June 4, 1991
    Assignee: Fujitsu Limited
    Inventors: Naoki Yokoyama, Toshio Fujii
  • Patent number: 5003360
    Abstract: A semiconductor functional element is composed of at least one bifurcated branch conductive path coplanar with a heterojunction in a semiconductor with a band discontinuity that produces a potential well, and at least two gate electrodes designed for digital operations and a common electrode facing each other. The gate electrodes cross both paths and the two gate electrodes are located outside of one path and the common electrode is located outside the other path so that electron wave conditions at the heterojunction are locally influenced by an electric field which can be changed by selecting a gate electrode to apply a voltage thereby forming a logic or a functional circuit.
    Type: Grant
    Filed: July 14, 1989
    Date of Patent: March 26, 1991
    Assignee: Fujitsu Limited
    Inventors: Makoto Okada, Naoki Yokoyama
  • Patent number: 4989052
    Abstract: A quantum effect semiconductor device a channel layer which is substantially a non-doped semiconductor and an n-type (or p-type) carrier supplying layer which is formed on a substrate and having a smaller electron affinity than the channel layer, and an n-type (or p-type) cap layer selectively formed on the carrier supplying layer so that an electron gas layer is formed only at a portion of the channel layer which is immediately under the cap layer.
    Type: Grant
    Filed: June 17, 1988
    Date of Patent: January 29, 1991
    Assignee: Fujitsu Limited
    Inventors: Makoto Okada, Naoki Yokoyama
  • Patent number: 4956681
    Abstract: A logic gate including a resonant-tunneling transistor and a resistor connected in series thereto. The resonant-tunneling transistor has a superlattice structure. The resonant-tunneling transistor may be a resonant-tunneling hot electron transistor or a resonant-tunneling bipolar transistor. The resonant-tunneling transistor conducts a current between a collector and an emitter. The current has one of at least three different current values in response to a base voltage of one of three different voltage values. The third current value is between the first and second current values, and a second voltage value is between the first and third voltage values. The logic gate outputs one of at least three states, a high state, a low state and a state approximately between the high and low states in response to a signal applied to the logic gate. The signal has an amplitude of one of the first to third voltage values. A logic circuit includes at least three connected resonant-tunneling transistors.
    Type: Grant
    Filed: February 15, 1989
    Date of Patent: September 11, 1990
    Assignee: Fujitsu Limited
    Inventors: Naoki Yokoyama, Masao Taguchi
  • Patent number: 4903090
    Abstract: A permeable base transistor includes a conductive type emitter layer; a conductive type base layer provided on the emitter layer, the emitter layer having a wider energy bandgap than the base layer; a conductive type collector layer; comb-shaped or lattice-shaped base electrodes formed adjacent to a heterojunction surface formed by the emitter layer and the base layer, the electrodes are provided through a Schottky junction or an insulating layer to the surrounding emitter, base, and collector layers.
    Type: Grant
    Filed: February 22, 1988
    Date of Patent: February 20, 1990
    Assignee: Fujitsu Limited
    Inventor: Naoki Yokoyama