Patents by Inventor Naoki Yokoyama

Naoki Yokoyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4889831
    Abstract: An electrode structure of an electrode of a refractory metal or a silicide thereof on a layer of In.sub.x Ga.sub.1-x As (0<x<1) on a substrate of a III-V compound semiconductor is ohmic and is stable even at a high temperature, for example, 900.degree. C. This high temperature stable ohmic electrode structure allows ion implantation into the substrate with the electrode as a mask followed by annealing to form a doped region in alignment with the edge of the electrode.
    Type: Grant
    Filed: November 30, 1987
    Date of Patent: December 26, 1989
    Assignee: Fujitsu Limited
    Inventors: Kazuaki Ishii, Toshiro Futatsugi, Toshio Oshima, Toshio Fujii, Naoki Yokoyama, Akihiro Shibatomi
  • Patent number: 4849934
    Abstract: A logic circuit including a resonant-tunneling transistor having a superlattice containing at least one quantum well layer, and a constant current source operatively connected between a base and an emitter of the transistor and supplying a constant current to said base. The transistor has a differential negative-resistance characteristic with at least one resonant point in a relationship between a current flowing in the base and a voltage between the base and emitter, and having at least two stable base current values at both sides of the resonant point on the characteristic, defined by the changeable base.multidot.emitter voltage. By supplying the base.multidot.emitter voltage having an amplitude of at least two amplitudes corresponding to the stable base current values, the transistor holds data corresponding to the base.multidot.emitter voltage.
    Type: Grant
    Filed: October 10, 1986
    Date of Patent: July 18, 1989
    Assignee: Fujitsu Limited
    Inventors: Naoki Yokoyama, Toshihiko Mori
  • Patent number: 4837178
    Abstract: A compound semiconductor (e.g., GaAs) IC device structure includes: a compound semiconductor substrate having a semi-insulating compound surface region; an active element laminated layer formed on the surface region; an isolation region of a semi-insulating (intrinsic) compound semiconductor which is filled in a groove extending into the surface region through the laminated layer; and active elements formed in regions of the laminated layer, isolated by the filled groove.
    Type: Grant
    Filed: September 4, 1987
    Date of Patent: June 6, 1989
    Assignee: Fujitsu Limited
    Inventors: Toshio Ohshima, Naoki Yokoyama
  • Patent number: 4821090
    Abstract: A compound semiconductor integrated circuit device including a heterojunction bipolar transistor and a field effect transistor. The heterojunction bipolar transistor has three compound semiconductor layers (type n-p-n or p-n-p) and makes a channel region or a channel-electron-supplying region of a field effect transistor with one of the three compound semiconductor layers.
    Type: Grant
    Filed: March 30, 1987
    Date of Patent: April 11, 1989
    Assignee: Fujitsu Limited
    Inventor: Naoki Yokoyama
  • Patent number: 4712121
    Abstract: A high-speed semiconductor device including an emitter layer a base layer a collector layer, a potential-barrier layer disposed between the base layer and the collector layer, and a superlattice disposed between the emitter layer and the base layer. The superlattice has at least one quantum well therein and has a low impedance state for tunneling carriers therethrough. Preferably, the high-speed semiconductor device may further include a graded layer disposed between the emitter layer and the superlattice. The graded layer has a conduction-energy level which is approximately equal to that of the emitter layer at the interface of the graded layer and the emitter layer and approximately equal to a predetermined conduction-energy level of the superlattice at the interface of the graded layer and the superlattice. In addition, the high-speed semiconductor device may act as a frequency multiplier, providing an output signal having 2.sup.
    Type: Grant
    Filed: July 12, 1985
    Date of Patent: December 8, 1987
    Assignee: Fujitsu Limited
    Inventor: Naoki Yokoyama
  • Patent number: 4617724
    Abstract: When the collector, base and emitter layers of a heterojunction bipolar transistor or a tunneling hot electron transistor are vertically stacked, the thickness of the base layer is preferably small so as to increase the current gain or switching speed. A thin base layer, however, has a disadvantage in that a space of the base layer between the actual base region and the base electrode makes the base resistance too large, decreasing current gain or switching speed, or is fully depleted due to interface states, making the transistor inoperable. This disadvantage is eliminated by forming a base contact region by doping in a region in alignment with the edge of an electrode so as to remove said space, that is, the base contact region is in contact with the actual base region.
    Type: Grant
    Filed: September 30, 1985
    Date of Patent: October 21, 1986
    Assignee: Fujitsu Limited
    Inventors: Naoki Yokoyama, Toshio Ohshima
  • Patent number: 4609903
    Abstract: A thin film resistor for use in microelectronic devices, the resistor having a resistive layer comprising silicon nitride (Si.sub.3 N.sub.4) and refractory metals of tungsten and/or molybdenum. The features of the structure of the resistor is that the film comprises a silicon nitride layer and grains of metal and/or metal silicide, wherein the resistivity is determined mainly by the silicon nitride. Therefore, the total resistance of the resistor can be controlled by controlling the amount of the silicon nitride, thus providing a wide range of the resistivity of 10.sup.-3 to 10.sup.9 .OMEGA.cm. Other characteristics such as immunity to the dopant contained in an adjacent doped layer, namely heat resistivity and low activation energy of the resistivity are verified by associated experiments.
    Type: Grant
    Filed: October 19, 1984
    Date of Patent: September 2, 1986
    Assignee: Fujitsu Limited
    Inventors: Nobuo Toyokura, Toyokazu Ohnishi, Naoki Yokoyama
  • Patent number: 4566021
    Abstract: A Schottky gate electrode of a refractory metal silicide is formed on a compound semiconductor, by which the barrier height is maintained satisfactorily even after heat treatment above 800.degree. C. Accordingly, it is possible to form an impurity diffused region using the Schottky gate electrode as a mask and then to effect the recrystallization of the semiconductor or the activation of the impurity by heat treatment, so that source and drain regions can be positioned by self-alignment relative to the gate electrode.
    Type: Grant
    Filed: April 10, 1985
    Date of Patent: January 21, 1986
    Assignee: Fujitsu Limited
    Inventor: Naoki Yokoyama
  • Patent number: 4522540
    Abstract: A method and an apparatus for removing a cutting burr produced when longitudinally fusion-cutting a slab and sticking to the lower surface of the slab along the fusion-cutting line, which comprise placing a slab having the cutting burr on a roller table comprising a plurality of rollers and horizontally extending with the lower surface having the cutting burr of the slab down so that the line of the cutting burr agrees with the travelling direction of the roller table; lifting a cutter of a burr cutting machine provided below the roller table to bring the cutter into contact with the lower surface having the cutting burr of the slab; horizontally moving the cutter toward the line of the cutting burr of the slab until the cutter passes the line of the cutting burr while keeping the contact with the lower surface of the slab, to cut off a part of the cutting burr by a length corresponding to the total length of a knife of the cutter by means of the knife of the cutter, and, horizontally pulling the cutter back
    Type: Grant
    Filed: March 16, 1983
    Date of Patent: June 11, 1985
    Assignee: Nippon Kokan Kabushiki Kaisha
    Inventors: Nobuhisa Hasebe, Hiroshi Kawada, Naoki Yokoyama, Shigeki Komori
  • Patent number: 4490496
    Abstract: A coating composition comprising (A) a thermoplastic resin having a glass transition temperature of 0.degree. to 80.degree. C., (B) a compound having 2 or more hydroxyl groups in the molecule, (C) a thixotropic agent and (D) a solvent, and said coating composition having a viscosity of 3 to 50 poises at 25.degree. C. and a thixotropy of 2 or more can give a moistureproof insulating coating film with uniform and large thickness and very few bubbles by one-time treatment over packing circuit boards.
    Type: Grant
    Filed: February 28, 1983
    Date of Patent: December 25, 1984
    Assignees: Hitachi Chemical Co., Ltd., Hitachi, Ltd.
    Inventors: Iwao Maekawa, Eiji Omori, Isao Uchigasaki, Hideyuki Tobita, Naoki Yokoyama, Seikichi Tanno, Fumio Nakano, Ren Ito