Abstract: A heat treatment jig by the invention comprising: the diameter of a disk-type structure being 60% or more of that of loaded semiconductor wafers; the thickness being 1.0 mm or more but 10 mm or less; the surface roughness Ra of 0.1 ?m or more but 100 ?m or less at a contacting surface with the wafers; and the surface planarity being specifically controlled in the concentric direction as well as in the diametrical direction, otherwise in place of above planarity, comprising a controlled maximum height in such a way that the maximum height is obtained by the flatness measurement at the multiple positions and the difference between said maximum height and the hypothetical-average-height-plane thus set is 50 ?m or less, can reduce the slip generation due to the close adhesion of the wafers and the jig.

Abstract: A heat treatment jig for supporting silicon semiconductor substrates by contacting, being loaded onto a heat treatment boat in a vertical heat treatment furnace, comprises; the configuration of a ring or a disc structure with the wall thickness between 1.5 and 6.0 mm; the deflection displacement of 100 ?m or less at contact region in loaded condition; the outer diameter which is 65% or more of the diameter of said substrate; and the surface roughness (Ra) of between 1.0 and 100 ?m at the contact region. The use of said jig enables to effectively retard the slip generation and to avoid the growth hindrance of thermally oxidized film at the back surface of said substrate, diminishing the surface steps causing the defocus in photolithography step in device fabrication process, thereby enabling to maintain high quality of silicon semiconductor substrates and to substantially enhance the device yield.

Abstract: This invention provides a heat treatment jig for semiconductor silicon substrates, which, in respective heat treatment of hydrogen annealing or argon annealing, can handle enlargement of the diameter of wafers to be treated and can also prevent slipping and dislocations that occur as a result of the stress caused by the weight of the wafer itself or the deflection of the heat treatment jig itself.

Abstract: An SOI substrate having a partial SOI structure in which a buried insulating film having a predetermined area is formed via an active layer in a part of a silicon single crystal substrate in plan view by ion-implanting elements to the part of the substrate and then applying thereto a thermal processing, wherein a thickness of a peripheral edge portion of said buried insulating film is getting thinner toward a terminal edge of said buried insulating film.

Abstract: When a two-division structure heat treatment jig for semiconductor substrate that includes a silicon first jig that comes into direct contact with a semiconductor substrate that is heat treated and supports the semiconductor substrate, and a second jig (holder) that holds the first jig and is mounted on a heat treatment boat is adopted as a heat treatment boat of a vertical heat treatment furnace, the stress concentrated during the heat treatment on a particular portion of the semiconductor substrate can be reduced; in the case of a semiconductor substrate large in the tare stress and having an outer shape of 300 mm being heat treated, or even in the case of the heat treatment being carried out under very high temperature conditions, the slips can be suppressed from occurring. The present invention can be widely applied as a stable heat treatment method of semiconductor substrates.

Abstract: A plurality of recessed portions having different depths is formed in a surface of the active layer wafer or in a bonding surface of the supporting substrate wafer. Those wafers are bonded to each other with an insulation film interposed therebetween. This allows a cavity of higher dimensional precision to be buried therein. A plurality of cavities may be formed simultaneously in a plurality of locations within the plane of the substrate, which allows the thickness of the SOI layer to be set arbitrarily. Accordingly, such a semiconductor device can be fabricated easily in which a MOS type element and a bipolar element are formed on the same chip in a mixed manner.

Abstract: An SOI substrate having a partial SOI structure in which a buried insulating film having a predetermined area is formed via an active layer in a part of a silicon single crystal substrate in plan view by ion-implanting elements to the part of the substrate and then applying thereto a thermal processing, wherein a thickness of a peripheral edge portion of said buried insulating film is getting thinner toward a terminal edge of said buried insulating film.

Abstract: An SOI substrate having a partial SOI structure in which a buried insulating film having a predetermined area is formed via an active layer in a part of a silicon single crystal substrate in plan view by ion-implanting elements to the part of the substrate and then applying thereto a thermal processing, wherein a thickness of a peripheral edge portion of said buried insulating film is getting thinner toward a terminal edge of said buried insulating film.

Abstract: An object of the present invention is to provide a single-crystal silicon wafer where octahedral voids of Grown-in defects, which are the generation source of COP on the surface and COP at several .mu.m depth of the surface layer of the single-crystal silicon wafer grown by the CZ method, are effectively eliminated, and a fabrication method of this wafer, where oxygen near the surface is out-diffused by annealing in a hydrogen and/or inactive gas ambient and oxide film on the inner walls of the octahedral voids near the surface are removed by the created unsaturated oxygen area, then oxidation annealing is performed in an oxygen ambient or mixed gas ambient of oxygen and inactive gas, so that interstitial silicon atoms are forcibly injected to completely eliminate the octahedral voids near the surface, and at the same time an IG layer is created in the bulk of the wafer.

Abstract: This invention anneals a vertical stack of two or more groups of unseparated wafers, with approximately 10 wafers in each group. The invention makes it possible to anneal more wafers in a single annealing operation under a variety of conditions, including: oxygen outer diffusion annealing to form a denuded zone; annealing to control bulk micro defects and provide intrinsic gettering functions; annealing to enhance gate oxide integrity by eliminating crystal-originated particles from the wafer surface and internal grown-in or as-grown defects; and suppression of dislocation and slip in elevated temperature environments.

Abstract: The present invention is designed to provide an annealing method for silicon single crystal wafers, which makes it possible to increase the number of silicon single crystal wafers processed during a single annealing process under a variety of annealing performed on silicon single crystal wafers, such as oxygen outer diffusion annealing for forming a DZ layer, annealing that generates and controls BMD for providing IG functions, and annealing that endeavors to improve and enhance GOI characteristics by eliminating wafer surface layer COP, and internal grown-in defects, and also enables the suppression of dislocation and slip in elevated temperature annealing environments. It calls for annealing to be performed by stacking up around 10 wafers, treating this group as a unit, placing this group, either horizontally or slightly inclined at an angle of roughly 0.5.about.5.degree.

Abstract: The present invention provides a method of manufacturing a semiconductor wafer whereby (1) deterioration of a micro-roughness in a low temperature range in hydrogen atmospheric treatment and increase of resistivity due to outward diffusion of an electrically active impurity in a high temperature range are prevented; (2) in the heat treatment in a hydrogen gas atmosphere, the concentration of gas molecules in the atmosphere, such as water, oxygen and the like, are brought to 5 ppm or less in water molecule conversion; and a reaction is suppressed in which a substrate surface is oxidized unequally and the micro-roughness deteriorates; and (3) the same kind of impurity as the electrically active impurity contained in a Si substrate is mixed into the atmosphere and the outward diffusion of the impurity in the vicinity of the Si substrate surface is prevented to prevent variation of the resistivity.