Abstract: In a semiconductor device having a heterojunction type superjunction structure, a drain portion and a source portion are electrically connected to one of a two-dimensional electron gas layer and a two-dimensional hole gas layer, and a gate portion is prevented by an insulating region from directly contacting the one of the two-dimensional election gas layer and the two-dimensional hole gas layer.

Abstract: In a semiconductor device having a heterojunction type superjunction structure, a drain portion and a source portion are electrically connected to one of a two-dimensional electron gas layer and a two-dimensional hole gas layer, and a gate portion is prevented by an insulating region from directly contacting the one of the two-dimensional election gas layer and the two-dimensional hole gas layer.

Abstract: In a predistortion type linearizer including a FET, an input matching circuit connected to the drain of the FET for receiving an input signal, an output matching circuit connected to the source of said the FET for outputting an output signal, and a inductor having a first terminal connected to the gate of the FET and a second terminal for receiving a first control voltage, a variable impedance circuit is connected to the second terminal of the inductor, and the impedance of the variable impedance circuit is adjusted by a second control voltage.

Abstract: Using a mask opening a gate region, an undoped GaAs layer is selectively etched with respect to an undoped Al0.2Ga0.8As layer by dry etching with introducing a mixture gas of a chloride gas containing only chlorine and a fluoride gas containing only fluorine (e.g. BCl3+SF6 or so forth). By about 100% over-etching is performed for the undoped GaAs layer, etching (side etching) propagates in transverse direction of the undoped GaAs layer. With using the mask, a gate electrode of WSi is formed. Thus, a gap in a width of about 20 nm is formed by etching in the transverse direction on the drain side of the gate electrode. By this, a hetero junction FET having reduced fluctuation of characteristics of an FET, such as a threshold value, lower a rising voltage and higher breakdown characteristics.

Abstract: An FET (Field Effect Transistor) has an epitaxial wafer including an Al0.2Ga0.8As gate contact layer. A GaAs gate buried layer doped with Si, Al0.2Ga0.8As wide-recess stopper layer doped with Si, an undoped GaAs layer and a GaAs cap layer doped with Si are sequentially formed on the gate contact layer by epitaxial growth. An electron accumulation layer is formed on the undoped GaAs layer and reduces a potential barrier. This allows electrons to pass through the potential barrier of the AlGaAs layer with higher probability. Because the GaAs layer is not doped with an impurity, electrons are scattered little and achieve higher mobility. It is therefore possible to reduce contact resistance from the cap layer to a channel layer. In addition, sheet resistance sparingly increases because the gate contact layer is not exposed to the outside. An ON resistance as low as 1.4 &OHgr;·mm is achievable which is lower than the conventional ON resistance by 0.2 &OHgr;·mm.

Abstract: The present invention provides a structure of a semiconductor device, the structure comprising: a compound semiconductor multi-layer structure having at least a channel region; and at least an ohmic contact layer provided adjacent to a first side face of the multi-layer structure, and the ohmic contact layer being in contact with at least a part of the first side face, wherein the ohmic contact layer has a top extending portion which extends in contact with a part of a top surface of the multi-layer structure.

Abstract: A hetero-junction FET has an intermediate layer including n-type-impurity doped layer between an electron supply layer and an n-type cap layer. The intermediate layer cancels the polarized negative charge generated between the electron supply layer and the n-type cap layer by ionized positive charge, thereby reducing the barrier against the electrons and source/drain resistance.

Abstract: The present invention provides a field effect transistor (FET) having, on a semi-insulating compound semiconductor substrate, a buffer layer; an active layer that includes a channel layer made of a first conductive-type epitaxial growth layer (e.g. InGaAs); source/drain electrodes formed on a first conductive-type contact layer which is formed either on said active layer or on a lateral face thereof; a gate layer made of a second conductive-type epitaxial growth layer (e.g. p+-GaAs); and a gate electrode formed on said gate layer; which further has, between said second conductive-type gate layer and said channel layer, a semiconductor layer (e.g. InGaP) that rapidly lowers the energy of the valance band spreading from said gate layer to said channel layer. The present invention improves withstand voltage characteristic of a FET having a pn junction in a gate region (JFET) and realizes stable operations of a JFET.

Abstract: In a predistortion type linearizer including a FET, an input matching circuit connected to the drain of the FET for receiving an input signal, an output matching circuit connected to the source of said the FET for outputting an output signal, and a inductor having a first terminal connected to the gate of the 1 FET and a second terminal for receiving a first control voltage, a variable impedance circuit is connected to the second terminal of the inductor, and the impedance of the variable impedance circuit is adjusted by a second control voltage.

Abstract: In order to form a first capacitor having a small capacitance and a second capacitor having a large capacitance on a substance with a minimum number of manufacturing steps, at least one of electrodes of the first capacitor and at least one of electrodes of the second capacitor are formed simultaneously.

Abstract: Using a mask opening a gate region, an undoped GaAs layer is selectively etched with respect to an undoped Al0.2Ga0.8As layer by dry etching with introducing a mixture gas of a chloride gas containing only chlorine and a fluoride gas containing only fluorine (e.g. BCl3+SF6 or so forth). By about 100% over-etching is performed for the undoped GaAs layer, etching (side etching) propagates in transverse direction of the undoped GaAs layer. With using the mask, a gate electrode of WSi is formed. Thus, a gap in a width of about 20 nm is formed by etching in the transverse direction on the drain side of the gate electrode. By this, a hetero junction FET having reduced fluctuation of characteristics of an FET, such as a threshold value, lower rising voltage and higher breakdown characteristics is obtained.

Abstract: An FET (Field Effect Transistor) has an epitaxial wafer including an Al0.2Ga0.8As gate contact layer. A GaAs gate buried layer doped with Si, Al0.2Ga0.8As wide-recess stopper layer doped with Si, an undoped GaAs layer and a GaAs cap layer doped with Si are sequentially formed on the gate contact layer by epitaxial growth. An electron accumulation layer is formed on the undoped GaAs layer and reduces a potential barrier. This allows electrons to pass through the potential barrier of the AlGaAs layer with higher probability. Because the GaAs layer is not doped with an impurity, electrons are scattered little and achieve higher mobility. It is therefore possible to reduce contact resistance from the cap layer to a channel layer. In addition, sheet resistance sparingly increases because the gate contact layer is not exposed to the outside. An ON resistance as low as 1.4 &OHgr;·mm is achievable which is lower than the conventional ON resistance by 0.2 &OHgr;·mm.

Abstract: A microwave amplifier circuit controls the output power thereof depending upon an associated transmitter of a wireless telephone, and a main amplifier transistor and switching transistors of a drain bias controlling circuit are implemented by gallium-arsenide heterojunction field effect transistors so that, even if they are integrated on a single compound semiconductor substrate, the microwave amplifier circuit achieves a high power efficiency over a wide output voltage range.

Abstract: An FET (Field Effect Transistor) has an epitaxial wafer including an Al0.2Ga0.8As gate contact layer. A GaAs gate buried layer doped with Si, Al0.2Ga0.8As wide-recess stopper layer doped with Si, an undoped GaAs layer and a GaAs cap layer doped with Si are sequentially formed on the gate contact layer by epitaxial growth. An electron accumulation layer is formed on the undoped GaAs layer and reduces a potential barrier. This allows electrons to pass through the potential barrier of the AlGaAs layer with higher probability. Because the GaAs layer is not doped with an impurity, electrons are scattered little and achieve higher mobility. It is therefore possible to reduce contact resistance from the cap layer to a channel layer. In addition, sheet resistance sparingly increases because the gate contact layer is not exposed to the outside. An ON resistance as low as 1.4 &OHgr;.mm is achievable which is lower than the conventional ON resistance by 0.2 &OHgr;.mm.

Abstract: A linear power amplifier includes a driver stage, employing an active feedforward-type predistorter, connected in cascade with a final power stage. The active feedforward-type predistorter has an amplifier with a predistorter connecting between its input and output. This driver stage has opposite gain and phase characteristics to that of the final power stage and is used to predistort an input signal. When combined with the final power stage, the nonlinear gain and phase of the power stage are compensated and linearized by the driver stage, resulting in a linear power amplifier with low distortion amplification and high efficiency operation.

Abstract: The present invention provides a linear power amplifier consists of a driver stage, employing an active feedforward-type predistorter, connected in cascade with a final power stage. The active feedforward-type predistorter consists of an amplifier with a predistorter connecting between its input and output. This driver stage has opposite gain and phase characteristics to that of the final power stage and is used to predistort an input signal. When combined with the final power stage, the nonlinear gain and phase of the power stage are compensated and linearized by the driver stage, resulting in a linear power amplifier with low distortion amplification and high efficiency operation.

Abstract: P-type impurities in a gate electrode is positively made to diffuse into a p-type impurity diffusion layer and an electrical p-n junction face in a gate electrode region is formed either within or on the bottom face of the p-type impurity diffusion layer, and thereby the effect that an interface state arising on a regrowth interface has over the p-n junction face can be well suppressed. This results in an improvement in high frequency characteristic of the JFET.

Abstract: A hetero-junction FET has an intermediate layer including n-type-impurity doped layer between an electron supply layer and an n-type cap layer. The intermediate layer cancels the polarized negative charge generated between the electron supply layer and the n-type cap layer by ionized positive charge, thereby reducing the barrier against the electrons and source/drain resistance.

Abstract: Using a mask opening a gate region, an undoped GaAs layer is selectively etched with respect to an undoped Al0.2Ga0.8As layer by dry etching with introducing a mixture gas of a chloride gas containing only chlorine and a fluoride gas containing only fluorine (e.g. BCl3+SF6 or so forth). By about 100% over-etching is performed for the undoped GaAs layer, etching (side etching) propagates in transverse direction of the undoped GaAs layer. With using the mask, a gate electrode of WSi is formed. Thus, a gap in a width of about 20 nm is formed by etching in the transverse direction on the drain side of the gate electrode. By this, a hetero junction FET having reduced fluctuation of characteristics of an FET, such as a threshold value, lower a rising voltage and higher breakdown characteristics.

Abstract: The present invention provides a structure of a semiconductor device, the structure comprising: a compound semiconductor multi-layer structure having at least a channel region; and at least an ohmic contact layer provided adjacent to a first side face of the multi-layer structure, and the ohmic contact layer being in contact with at least a part of the first side face, wherein the ohmic contact layer has a top extending portion which extends in contact with a part of a top surface of the multi-layer structure.