Abstract: The present invention provides a field effect transistor (FET) having, on a semi-insulating compound semiconductor substrate, a buffer layer; an active layer that includes a channel layer made of a first conductive-type epitaxial growth layer (e.g. InGaAs); source/drain electrodes formed on a first conductive-type contact layer which is formed either on said active layer or on a lateral face thereof; a gate layer made of a second conductive-type epitaxial growth layer (e.g. p+-GaAs); and a gate electrode formed on said gate layer; which further has, between said second conductive-type gate layer and said channel layer, a semiconductor layer (e.g. InGaP) that rapidly lowers the energy of the valance band spreading from said gate layer to said channel layer. The present invention improves withstand voltage characteristic of a FET having a pn junction in a gate region (JFET) and realizes stable operations of a JFET.

Abstract: A method for manufacturing a semiconductor device having a metal-insulator-metal (MIM) capacitor comprises the steps of forming a first dielectric film on a substrate, forming a MIM capacitor on the first dielectric film, forming a second dielectric film covering the MIM capacitor, selectively removing the first and second dielectric films to expose the substrate surface, surface treating using a hydrochloric acid solution, forming a third dielectric film on the second dielectric film and the substrate, and forming a transistor on the third dielectric film. The second dielectric film protects the capacitor insulator film of the MIM capacitor.

Abstract: A matching circuit is formed by a series inductor, a parallel capacitor, a drain bias circuit, and a DC-blocking capacitor for the purpose of impedance matching. A capacitor having a capacitance that is dependent upon the bias voltage is used as the parallel capacitor. This can be, for example, a material such as a (Ba.sub.X Sr.sub.1-X)TiO.sub.3 thin-film, which exhibits a capacitance having a bias voltage dependency. Because this thin-film capacitor exhibits polarization by an electrical field, its capacitance is the largest with a bias of 0 volts, and is reduced to approximately 50% as the bias voltage is increased. By using this capacitor in a matching circuit, it is possible to change the matching condition as the output power is increased, that is, as the voltage applied to the capacitor is increased.

Abstract: A passive element circuit is formed by a spiral inductor, a high-dielectric-constant thin-film capacitor, a via hole, and a bonding pad. By using SrTiO.sub.3 as the high-dielectric-constant thin-film, which exhibits a dielectric constant of 200 up to a frequency of 20 GHz, it is possible to achieve a reduction of the capacitor surface area to approximately 1/30 of the area formerly required when using a SiN.sub.x (dielectric constant up to 6.5). Two high-dielectric-constant thin-film capacitors, a via hole for grounding, and a bonding pad are disposed at the center, which are surrounded by the spiral inductor. To connect the two high-dielectric-constant thin-film capacitors are joined in series, they are formed on one high-dielectric-constant thin-film. A lead from the spiral inductor is made by a metal wire from the bonding pad at the center.

Abstract: In a method of manufacturing a semiconductor device, the InP substrate is subjected to a NH.sub.3 plasma processing by a plasma CVD apparatus into which NH.sub.3 gas is introduced. The InP oxide film is deoxided and removed therefrom and an InN (nitride) film is then formed thereon. S.sub.i H.sub.3 gas and NH.sub.3 gas are introduced into the plasma CVD apparatus to form a SiNx spacer layer on the InN (nitride) film. A source electrode and drain electrode are formed as ohmic electrodes. A Pt layer is stacked on the InP channel region by evaporation lift-off or ion beam sputter method to form a gate electrode. Thereafter, by a process similar to that of forming the SiNx/InN spacer layer, a SiNx/InN passivation film is formed on all over the InP substrate including the source electrode, the drain electrode, and the gate electrode. Accordingly, a semiconductor device protected by the passivation film is completed.

Abstract: In a method manufacturing a semiconductor device, a semiconductor layer having a device forming region is formed on substrate. Next, a region except for the device forming region is changed into an insulator. In this case, a conducting path is left across the semiconductor device to electrically connect the semiconductor device with an adjacent semiconductor device. Subsequently, the device forming region is etched on the condition that the conducting path is left. Finally, the conducting path is disrupted after the etching process. Thus, the semiconductor device and the adjacent semiconductor device are left in an electrical contact via the conducting path during the etching process. Consequently, the uniformity of the etching between the semiconductor devices is largely improved.

Abstract: The depletion mode two-dimensional electron gas field effect transistor comprises a substantially pure semiconductor layer, an impurity doped super lattice semiconductor layer formed on the pure semiconductor layer, the energy band gaps and the electron affinities of the pure semiconductor layer and the super lattice semiconductor layer being selected to produce the two-dimensional electron gas at the surface of the pure semiconductor layer when no bias is applied to the super lattice semiconductor layer, source and drain regions formed separatedly in the super lattice semiconductor layer to reach the pure semiconductor layer, a gate electrode formed on the super lattice semiconductor layer between the source and drain regions, and large energy band gap regions formed at side portions of the gate electrode which do not face the source and drain regions, the large energy band gap regions having an energy band gap larger than the super lattice semiconductor layer and being formed by local annealing to convert t