Abstract: A semiconductor device is provided, which aims to reduce the standby power thereof by reducing the leak between a body and a drain with restraining the effect on a threshold voltage, in order to actualize the highly reliable semiconductor device. When extension regions are formed, an n-type impurity less diffusive than phosphorus (P+), for example, arsenic (As+) is used as an impurity. In addition to ordinary ion implantation with high dose (high concentration) and low acceleration energy, As+ ions are implanted with low dose and high acceleration energy.

Abstract: A P-type pocket layer is formed in the surficial portion of a semiconductor substrate, a sidewall insulating film having a thickness of as thin as 10 nm or around is formed, and P is implanted therethrough to thereby form an N-type extension layer in the surficial portion of the p-type pocket layer. Then, a sidewall insulating film is formed, and P is implanted to thereby form an N-type source and a drain diffusion layer. P, having a larger coefficient of diffusion than that of conventionally-used As, used in the formation of the pocket layer can successfully moderate a strong electric field in the vicinity of the channel, and can consequently reduce leakage current between the drain and the semiconductor substrate and thereby reduce the off-leakage current, even if the gate length is reduced to 100 nm or shorter.

Abstract: A tunneling insulating film is formed on the partial surface area of a semiconductor substrate. A floating gate electrode is formed on the tunneling insulating film. A gate insulating film covers the side wall of the floating gate electrode and a partial surface area of the semiconductor substrate on both sides of the floating gate electrode. A first control gate electrode is disposed on the gate insulating film over the side wall of the floating gate electrode and over a partial surface area of the semiconductor substrate on both sides of the floating gate electrode. A pair of impurity doped regions is formed in a surface layer of the semiconductor substrate on both sides of a gate structure including the floating gate structure and first control gate structure.

Abstract: A P-type pocket layer is formed in the surficial portion of a semiconductor substrate, a sidewall insulating film having a thickness of as thin as 10 nm or around is formed, and P is implanted therethrough to thereby form an N-type extension layer in the surficial portion of the p-type pocket layer. Then, a sidewall insulating film is formed, and P is implanted to thereby form an N-type source and a drain diffusion layer. P, having a larger coefficient of diffusion than that of conventionally-used As, used in the formation of the pocket layer can successfully moderate a strong electric field in the vicinity of the channel, and can consequently reduce leakage current between the drain and the semiconductor substrate and thereby reduce the off-leakage current, even if the gate length is reduced to 100 nm or shorter.

Abstract: A non-volatile semiconductor memory comprising a semiconductor substrate, a gate insulating film formed on the substrate, and having a thin central section and thick end sections, a floating gate formed on the rate insulating film, an inter-electrode insulating film formed on the floating gate, a control gate formed on the inter-electrode insulating film, and source/drain regions formed in the substrate on both sides of the floating sate and having extensions extending under the thick end sections of the floating gate, and separated from the thin central section of the gate insulating film, wherein the thin central section enables tunneling of carriers at a low applied voltage, and thick end sections prevent tunneling of stored charges to the extensions and enhance retention of the stored charges.

Abstract: A method and device for converting light from a first wavelength to a second wavelength. The method comprises the steps of exciting an electron in a quantum dot with an incident infrared photon having the first wavelength, the excited electron having a first energy, tunneling the excited electron through a barrier into a stress induced quantum dot, and recombining the excited electron with a hole in the stress induced quantum dot, therein producing a photon having the second wavelength, typically in the visible range.

Abstract: A glass panel, its manufacturing method and a spacer for use in the glass panel. In the glass panel, a plurality of spacers (3) are formed between and along a first opposing face (2A) of a first glass sheet (1A) and a second opposing face (2B) of a second glass sheet (1B) so as to form a space (C) therebetween, and a sealing material (6) is provided at peripheral edge (1a) of the first glass sheet (1A) and the second glass sheet (1B) for maintaining the space (C) gas-tight. The plurality of such spacers (3) having, at one side thereof, contact portions (5) capable of coming into contact with the first opposing face (2A) are provided on the second opposing face (2B). The contact portions (5) and the first opposing face (2A) are movable relative to each other.

Abstract: To provide a semiconductor device which can retain information for a long period of time even in a case that the tunnel insulation film is thin. A semiconductor device comprises a first insulation film 14 formed on a semiconductor substrate 10, a floating gate electrode 22 formed on the first insulation film, a second insulation 24 film formed on the floating gate electrode, and a control gate electrode 26 formed on the second insulation film. A depletion layer is formed in the floating gate electrode near the first insulation film in a state that no voltage is applied between the floating gate electrode and the semiconductor substrate.

Abstract: A glass panel including a pair of first and second glass sheets (1A, 1B) disposed with sheet faces thereof opposed to each other, a plurality of spacers (5) being interposed between the pair of glass sheets (1A, 1B) for forming a space (4) therebetween; and a sealing material (S) for bonding peripheral edges (3) of the glass sheets (1A, 1B) together for sealing the space (4), the sealing material having a lower fusing temperature than the softening point of the glass sheets (1A, 1B). Each spacer (5) is formed by disposing spacer-forming paste (11) in a predetermined shape on the sheet face of the glass sheet (1A, 1B). Or, the spacer (5) comprises a plurality of spacer bodies (51) two-dimensionally interconnected to each other via a connecting member (52).

Abstract: A semiconductor memory device manufacturing method includes the steps of (a) forming a stack of a first gate insulating layer, a floating gate electrode layer, an inter-electrode insulating layer, and a control electrode layer on a semiconductor substrate; (b) patterning the stack using a mask and thereby creating a gate electrode pattern; (c) causing a chemical reaction for the gate electrode pattern from both sides thereof and increasing thereby the thickness of the gate insulating layer at the end sections; and (d) implanting ions of impurity in the active regions on both sides of the gate electrode pattern and forming thereby first source/drain regions respectively extending into regions respectively below the end sections of the gate insulating layer. In the semiconductor memory device, a tunnel oxide film can be thinned and reduction in retention time of memory information can be prevented.

Abstract: A glass panel including a pair of first and second glass sheets (1A, 1B) disposed with sheet faces thereof opposed to each other, a plurality of spacers (5) being interposed between the pair of glass sheets (1A, 1B) for forming a space (4) therebetween; and a sealing material (S) for bonding peripheral edges (3) of the glass sheets (1A, 1B) together for sealing the space (4), the sealing material having a lower fusing temperature than the softening point of the glass sheets (1A, 1B). Each spacer (5) is formed by disposing spacer-forming paste (11) in a predetermined shape on the sheet face of the glass sheet (1A, 1B). Or, the spacer (5) comprises a plurality of spacer bodies (51) two-dimensionally interconnected to each other via a connecting member (52).

Abstract: A ferromagnetic tunnel junction random access memory includes a ferromagnetic tunnel junction structure including a first ferromagnetic layer, a second ferromagnetic layer disposed adjacent to the first ferromagnetic layer and having a fixed magnetization, and a tunnel insulator layer interposed between the first and second ferromagnetic layers; a conductor plug penetrating the first ferromagnetic layer, the tunnel insulator layer and the second ferromagnetic layer along a center axis; a first selection line coupled to a first end of the conductor plug; and a second selection line coupled to a second end of the conductor plug opposite to the first end. The first ferromagnetic layer has a generally ring shape surrounding the conductor plug and is insulated from the conductor plug. One of the first and second ferromagnetic layers has an antiferromagnetic layer pattern on a portion thereof.

Abstract: To provide a semiconductor device which can retain information for a long period of time even in a case that the tunnel insulation film is thin. A semiconductor device comprises a first insulation film 14 formed on a semiconductor substrate 10, a floating gate electrode 22 formed on the first insulation film, a second insulation 24 film formed on the floating gate electrode, and a control gate electrode 26 formed on the second insulation film. A depletion layer is formed in the floating gate electrode near the first insulation film in a state that no voltage is applied between the floating gate electrode and the semiconductor substrate.

Abstract: A tunneling insulating film is formed on the partial surface area of a semiconductor substrate. A floating gate electrode is formed on the tunneling insulating film. A gate insulating film covers the side wall of the floating gate electrode and a partial surface area of the semiconductor substrate on both sides of the floating gate electrode. A first control gate electrode is disposed on the gate insulating film over the side wall of the floating gate electrode and over a partial surface area of the semiconductor substrate on both sides of the floating gate electrode. A pair of impurity doped regions is formed in a surface layer of the semiconductor substrate on both sides of a gate structure including the floating gate structure and first control gate structure.

Abstract: In a double glazing including a pair of glass sheets 1, a plurality of spacers 2 disposed between opposed sheet faces of the glass sheets 1 by a predetermined pitch, and a sealing member 4 interposed between the glass sheets 1 along the entire peripheries thereof, with a space V between the glass sheets being sealed in a vacuum condition, each spacer 2 is formed so as to maintain a predetermined distance between the glass sheets when subjected to a static normal external pressure normally applied thereto in the direction of sheet thickness and also to relieve stress through plastic deformation when subjected to an impact dynamically applied in the sheet thickness direction.

Abstract: A single-electron device includes a substrate, an insulating film provided on the substrate, a plurality of nanometer-size conductive particles formed in the insulating film along an interface between the substrate and the insulating film, and an electrode provided on the insulating film, wherein the conductive particles have a generally identical size and arranged substantially in a plane at a depth closer to the substrate.

Abstract: A wavelength-domain-multiplication memory comprises a first semiconductor layer including a first conductivity type impurity, a carrier barrier semiconductor layer formed on the first semiconductor layer, and quantum dots formed in the carrier barrier semiconductor layer.

Abstract: A photo hole burning memory device includes a quantum dot and a quantum well layer cooperating with the quantum dot for storing information and a periodic structure that creates a photonic bandgap, wherein the periodic structure includes a local irregularity that forms a level in the photonic bandgap.

Abstract: A grommet for automatic insertion into a mounting hole in a panel by a robot including a head portion 1 having a longitudinal bore for receiving a screw through its center, a bottom portion 3 including a stepped portion 7 elastically engaging the robot arm located within the longitudinal bore; and locking claws 4 attached to the grommet which reflect during insertion of the grommet into the mounting hole and then spring snap into engagement when the locking claws 4 clear the mounting hole, such that the force required to disengage the robot arm 5 from the stepped portion 7 is less than the force required to extract the grommet from the panel, which enables the robot to easily determine whether or not the grommet is accurately inserted into the mounting hole.