Patents by Inventor Naoto Jikutani

Naoto Jikutani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Verticle-cavity, surface-emission type laser diode and fabrication process thereof
    Publication number: 20020074631
    Abstract: A vertical-cavity, surface-emission-type laser diode includes an optical cavity formed of an active region sandwiched by upper and lower reflectors, wherein the lower reflector is formed of a distributed Bragg reflector and a non-optical recombination elimination layer is provided between an active layer in the active region and the lower reflector.
    Type: Application
    Filed: September 20, 2001
    Publication date: June 20, 2002
    Applicant: Ricoh Company, Ltd.
    Inventors: Shunichi Sato, Takashi Takahashi, Naoto Jikutani, Morimasa Kaminishi, Akihiro Itoh
  • Light emitting devices with layered III-V semiconductor structures, and modules and systems for computer, network and optical communication, using such device
    Publication number: 20010030319
    Abstract: A semiconductor light emitting device is disclosed, including a semiconductor substrate, an active region comprising a strained quantum well layer, and a cladding layer for confining carriers and light emissions, wherein the amount of lattice strains in the quantum well layer is in excess of 2% against either the semiconductor substrate or cladding layer and, alternately, the thickness of the quantum well layer is in excess of the critical thickness calculated after Matthews and Blakeslee.
    Type: Application
    Filed: December 12, 2000
    Publication date: October 18, 2001
    Inventors: Shunichi Sato, Takashi Takahashi, Naoto Jikutani
  • Light emitting devices with layered III-V semiconductor structures
    Patent number: 6207973
    Abstract: A semiconductor light emitting device is disclosed, including a semiconductor substrate, an active region comprising a strained quantum well layer, and a cladding layer for confining carriers and light emissions, wherein the amount of lattice strains in the quantum well layer is in excess of 2% against either the semiconductor substrate or cladding layer and, alternately, the thickness of the quantum well layer is in excess of the critical thickness calculated after Matthews and Blakeslee.
    Type: Grant
    Filed: August 19, 1999
    Date of Patent: March 27, 2001
    Assignee: Ricoh Company, Ltd.
    Inventors: Shunichi Sato, Takashi Takahashi, Naoto Jikutani