Abstract: In a method of manufacturing a semiconductor device, a body region is formed in an epitaxial layer provided on a semiconductor substrate. A part of a semiconductor material forming the body region surface is removed to form a convex-type contact region protruding from the body region surface and to form a shallow trench surrounding the convex-type contact region. A deep trench region is formed so as to extend from the shallow trench surface to inside of the epitaxial layer. A gate insulating film is formed on an inner wall of the deep trench region which is filled with polycrystalline silicon that is held in contact with the gate insulating film. A source region and a body contact region are formed in the shallow trench and the convex-type contact region, respectively, and a silicide layer is formed to connect the source region and the body contact region to each other.

Abstract: Provided is a semiconductor capacitor including: a capacitor device forming region having a trapezoidal trench which is formed on a surface of a first conductivity type semiconductor substrate; a second conductivity type lower electrode layer provided along the trapezoidal trenches of the capacitor device forming region; a capacitor insulating film formed at least on a surface of the second conductivity type lower electrode layer; and a second conductivity type upper electrode formed on a surface of the capacitor insulating film.

Abstract: Provided is a method of manufacturing a trench MOSFET through use of a simple process having good controllability, which is capable of forming the trench MOSFET on the same substrate as a CMOS transistor and capable of reducing the element area. The method of manufacturing a trench MOSFET includes a formation of a three-dimensional body contact region. Thus, the trench MOSFET can have a structure which can ensure a contact similar to that in a conventional case even in a smaller area.

Abstract: To realize forming a trench MOSFET in which a depth of a P-body is changed on the same surface as a CMOS by employing steps with good controllability and without greatly increasing the number of manufacturing steps, provided is a trench MOSFET including an extended body region (10), which is a part of a P-body region (4) and is provided in a vicinity of a deep trench (5) with a distance, the extended body region (10) being diffused deeper than the P-body region (4).

Abstract: Provided is a semiconductor capacitor including: a capacitor device forming region having a trapezoidal trench which is formed on a surface of a first conductivity type semiconductor substrate; a second conductivity type lower electrode layer provided along the trapezoidal trenches of the capacitor device forming region; a capacitor insulating film formed at least on a surface of the second conductivity type lower electrode layer; and a second conductivity type upper electrode formed on a surface of the capacitor insulating film.

Abstract: Provided is a semiconductor capacitor including: a capacitor device forming region having a trapezoidal trench which is formed on a surface of a first conductivity type semiconductor substrate; a second conductivity type lower electrode layer provided along the trapezoidal trenches of the capacitor device forming region; a capacitor insulating film formed at least on a surface of the second conductivity type lower electrode layer; and a second conductivity type upper electrode formed on a surface of the capacitor insulating film.

Abstract: In a method of manufacturing a high withstanding voltage MOSFET, a region to be doped with impurities and a region to be doped with no impurity are provided when ion implantation of the impurities is performed in the channel forming region, for controlling a threshold voltage. The region to be doped with no impurity is suitably patterned so that impurity concentration of the channel forming region near boundaries between a well region and a source region and between the well region and a drain region having the same conductivity type as the well region may be increased, to thereby induce a reverse short channel effect. By canceling a short channel effect with the reverse short channel effect induced by the above-mentioned method, the short channel effect of the high withstanding voltage MOSFET may be suppressed.

Abstract: To realize forming a trench MOSFET in which a depth of a P-body is changed on the same surface as a CMOS by employing steps with good controllability and without greatly increasing the number of manufacturing steps, provided is a trench MOSFET including an extended body region (10), which is a part of a P-body region (4) and is provided in a vicinity of a deep trench (5) with a distance, the extended body region (10) being diffused deeper than the P-body region (4).

Abstract: Provided is a semiconductor capacitor including: a capacitor device forming region having a trapezoidal trench which is formed on a surface of a first conductivity type semiconductor substrate; a second conductivity type lower electrode layer provided along the trapezoidal trenches of the capacitor device forming region; a capacitor insulating film formed at least on a surface of the second conductivity type lower electrode layer; and a second conductivity type upper electrode formed on a surface of the capacitor insulating film.

Abstract: Provided is a manufacturing method for a power management semiconductor device or an analog semiconductor device both including a CMOS. According to the method, a substance having high thermal conductivity is additionally provided above a semiconductor region constituting a low impurity concentration drain region so as to expand the drain region, which contributes to a promotion of thermal conductivity (or thermal emission) in the drain region during a surge input and leads to suppression of local temperature increase, to thereby prevent thermal destruction. Therefore, it is possible to manufacture a power management semiconductor device or an analog semiconductor device with the extended possibility of transistor design.

Abstract: A semiconductor integrated circuit device has an SOI substrate comprising an insulating film laminated on a semiconductor support substrate and a semiconductor thin film laminated on the insulating film. A first N-channel MOS transistor, a first P-channel MOS transistor, and a resistor are each disposed on the semiconductor thin film. A second N-channel MOS transistor serving as an electrostatic discharge (ESD) protection element is disposed on a surface of the semiconductor support substrate that is exposed by removing a part of the semiconductor thin film and a part of the insulating film. The second N-channel MOS transistor has a gate electrode, a source region and a drain region surrounding the source region through the gate electrode to maintain a constant distance between the drain region and the source region.

Abstract: In a method of manufacturing a high withstanding voltage MOSFET, a region to be doped with impurities and a region to be doped with no impurity are provided when ion implantation of the impurities is performed in the channel forming region, for controlling a threshold voltage. The region to be doped with no impurity is suitably patterned so that impurity concentration of the channel forming region near boundaries between a well region and a source region and between the well region and a drain region having the same conductivity type as the well region may be increased, to thereby induce a reverse short channel effect. By canceling a short channel effect with the reverse short channel effect induced by the above-mentioned method, the short channel effect of the high withstanding voltage MOSFET may be suppressed.

Abstract: In a manufacturing method for a semiconductor device, a first impurity diffusion layer for a low impurity concentration drain of a second conductivity type is formed within a semiconductor layer of a first conductivity type, and a second impurity diffusion layer for a high impurity concentration drain of the second conductivity type is formed adjacent to the first impurity diffusion layer, with the second impurity diffusion layer having a higher impurity concentration than the first impurity diffusion layer. An interlayer insulating film is formed on the semiconductor substrate layer. A drain extension region having a high thermal conductivity is formed on a surface of the first impurity diffusion layer. A contact hole is formed through the interlayer insulating film and up to the second impurity diffusion layer.

Abstract: In a protection NMOS transistor serving as an ESD input/output protection element formed on a semiconductor support substrate, a drain region of the N-type protection transistor is formed so as to surround the source region, and a minimum distance between the source and the drain is kept constant, which makes it possible to ensure a sufficient ESD breakdown strength and to realize a structure capable of protecting input/output terminal, particularly an output terminal, of the fully depleted SOI CMOS device vulnerable to ESD noise.

Abstract: Provided is a manufacturing method for a power management semiconductor device or an analog semiconductor device both including a CMOS. According to the method, a substance having high thermal conductivity is additionally provided above a semiconductor region constituting a low impurity concentration drain region so as to expand the drain region, which contributes to a promotion of thermal conductivity (or thermal emission) in the drain region during a surge input and leads to suppression of local temperature increase, to thereby prevent thermal destruction. Therefore, it is possible to manufacture a power management semiconductor device or an analog semiconductor device with the extended possibility of transistor design.

Abstract: An N-channel MOS transistor of a semiconductor device having a high withstand voltage employs a drain structure with a low concentration and a large diffusion depth, which causes a problem in that a sufficiently high withstand voltage cannot be obtained due to a parasitic NPN transistor formed among the drain, the well, and the semiconductor substrate which are arranged in the stated order.

Abstract: An N-channel MOS transistor of a semiconductor device having a high withstand voltage employs a drain structure with a low concentration and a large diffusion depth, which causes a problem in that a sufficiently high withstand voltage cannot be obtained due to a parasitic NPN transistor formed among the drain, the well, and the semiconductor substrate which are arranged in the stated order.

Abstract: When a bipolar transistor having a buried layer is formed, the withstanding pressure of the bipolar transistor is deteriorated by upward diffusion to a great extent from the buried layer. When a buried layer is formed in a semiconductor substrate, by providing a region without impurity introduction, upward diffusion from the buried layer is controlled to prevent deterioration in the withstanding pressure.

Abstract: A semiconductor integrated circuit device comprises at least two MISFETs formed on a semiconductor substrate and connected in series in a diode connection. Each of the MISFETs has a source, a drain, a channel extending between the source and the drain, and a gate disposed over the channel through a gate insulating film. One of the MISFETs has a first threshold voltage, and the other of the MISFETs has a second threshold voltage lower than the first threshold voltage. A portion of the channel of the semiconductor substrate of each of the MISFETs has an impurity concentration equal to or less than 6.times.10.sup.14 atoms/cc.