MISFET semiconductor integrated circuit device
A semiconductor integrated circuit device comprises at least two MISFETs formed on a semiconductor substrate and connected in series in a diode connection. Each of the MISFETs has a source, a drain, a channel extending between the source and the drain, and a gate disposed over the channel through a gate insulating film. One of the MISFETs has a first threshold voltage, and the other of the MISFETs has a second threshold voltage lower than the first threshold voltage. A portion of the channel of the semiconductor substrate of each of the MISFETs has an impurity concentration equal to or less than 6.times.10.sup.14 atoms/cc.
Latest Seiko Instruments Inc. Patents:
Claims
1. A semiconductor integrated circuit device comprising: a first MISFET and a second MISFET both formed on a semiconductor substrate and connected in series in a diode connection, each of the first and second MISFETs having a source, a drain, a channel disposed between the source and the drain, and a gate disposed over the channel through a gate insulating film, the first MISFET having a first threshold voltage, and the second MISFET having a second threshold voltage lower than the first threshold voltage; wherein a portion of the semiconductor substrate at the channel region of each of the MISFETs has an impurity concentration equal to or less than 6.times.10.sup.14 atoms/cc.
2. A semiconductor integrated circuit device comprising: a first MISFET and a second MISFET both formed on a semiconductor substrate and connected in series in a diode connection, each of the first and second MISFETs having a source, a drain, a channel disposed between the source and the drain, and a gate disposed over the channel through a gate insulating film, the first MISFET having a first threshold voltage, and the second MISFET having a second threshold voltage lower than the first threshold voltage; wherein the drain and the gate of the first MISFET are connected to a first node, the drain and the gate of the second MISFET are connected to a second node, the source of the first MISFET is connected to the second node, a first input signal having a first phase is inputted to the first node via a capacitance element, a second input signal having a second phase different from the first phase of the first input signal is inputted to the second node via a capacitance element, and an input voltage applied to the first node is outputted from the source of the second MISFET after boosting the first input voltage.
3. A semiconductor integrated circuit device comprising: a first MISFET and a second MISFET both formed on a semiconductor substrate and connected in series in a diode connection, each of the first and second MISFETs having a source, a drain, a channel disposed between the source and the drain, and a gate disposed over the channel through a gate insulating film, the first MISFET having a first threshold voltage, and the second MISFET having a second threshold voltage lower than the first threshold voltage; wherein a first impurity concentration at a portion of the semiconductor substrate between the source and the drain of the first MISFET is higher than a second impurity concentration at a portion of the semiconductor substrate between the source and the drain of the second MISFET.
4. A semiconductor integrated circuit device comprising: a first MISFET and a second MISFET both formed on a semiconductor substrate and connected in series in a diode connection, each of the first and second MISFETs having a source, a drain, a channel disposed between the source and the drain, and a gate disposed over the channel through a gate insulating film, the first MISFET having a first threshold voltage, and the second MISFET having a second threshold voltage lower than the first threshold voltage; wherein a length of the channel of the first MISFET is larger than a length of the channel of the second MISFET.
5. A semiconductor integrated circuit device comprising: a first MISFET and a second MISFET both formed on a semiconductor substrate and connected in series in a diode connection, each of the first and second MISFETs having a source, a drain, a channel disposed between the source and the drain, and a gate disposed over the channel through a gate insulating film, the first MISFET having a first threshold voltage, and the second MISFET having a second threshold voltage lower than the first threshold voltage; wherein the gate insulating film of each of the first and second MISFETs comprises a first gate insulating film having a first thickness and a second gate insulating film having a second thickness smaller than the first thickness, the first gate insulating film and the second gate insulating film of each of the first and second MISFETs extending in a length direction of the channel of the first MISFET and the second MISFET, respectively, and a channel length of a total of the channel prescribed by the first gate insulating film of the first MISFET is shorter than a channel length of a total of the channel prescribed by the first gate insulating film of the second MISFET.
6. A semiconductor integrated circuit device comprising: a first MISFET and a second MISFET both formed on a semiconductor substrate and connected in series in a diode connection, each of the first and second MISFETs having a source, a drain, a channel disposed between the source and the drain, and a gate disposed over the channel through a gate insulating film, the first MISFET having a first threshold voltage, and the second MISFET having a second threshold voltage lower than the first threshold voltage; wherein the gate insulating film of each of the first and the second MISFETs comprises a first gate insulating film having a first thickness and a second gate insulating film having a second thickness smaller than the first thickness, the first gate insulating film and the second gate insulating film of each of the first and second MISFETs extending in a length direction of the channel of the first MISFET and the second MISFET, respectively, and a first channel length of a total of the channel prescribed by the second gate insulating film of the first MISFET is larger than a second channel length of a total of the channel prescribed by the second gate insulating film of the second MISFET.
7. A semiconductor integrated circuit device according to claim 5; wherein the gate comprises a first gate disposed on the first gate insulating film; and further comprising a second gate disposed on the second gate insulating film, the first and second gates being formed separately and independently from each other.
8. A semiconductor integrated circuit device having a voltage boosting circuit, comprising: a plurality of MISFETs connected together in a diode connection, each of the MISFETs being formed on a semiconductor substrate and having a source, a drain and a channel region disposed between the source and the drain, a portion of the semiconductor substrate at the channel region having an impurity concentration equal to or less than 6.times.10.sup.14 atoms/cc.
9. A semiconductor integrated circuit device comprising: at least two MISFETs formed on a semiconductor substrate and connected in series in a diode connection, each of the MISFETs having a source, a drain, a channel extending between the source and the drain, a first gate insulating film disposed over the channel, a first gate formed over the first gate insulating film, a second gate insulating film disposed over the channel, and a second gate disposed over the second gate insulating film and formed separately and independently from the first gate, the first gate insulating film having a thickness greater than a thickness of the second gate insulating film.
RE35121 | December 12, 1995 | Olivd et al. |
4471373 | September 11, 1984 | Shimizu et al. |
4488061 | December 11, 1984 | Mukawa et al. |
4651406 | March 24, 1987 | Shimizu et al. |
4740714 | April 26, 1988 | Masaki et al. |
4866002 | September 12, 1989 | Shizukuishi et al. |
5006974 | April 9, 1991 | Kazerounian et al. |
5081371 | January 14, 1992 | Wong |
5285069 | February 8, 1994 | Kaibara et al. |
5317179 | May 31, 1994 | Chen et al. |
5362981 | November 8, 1994 | Sato et al. |
5475335 | December 12, 1995 | Merrill et al. |
5495122 | February 27, 1996 | Tada |
5497021 | March 5, 1996 | Tada |
5499183 | March 12, 1996 | Kubatake |
0228387 | October 1985 | DDX |
3107543 | December 1981 | DEX |
2633557 | February 1978 | JPX |
0123676 | October 1978 | JPX |
56-162861 | December 1981 | JPX |
57-24567 | February 1982 | JPX |
0006175 | January 1983 | JPX |
0231869 | December 1984 | JPX |
0091676 | May 1985 | JPX |
0248256 | October 1987 | JPX |
0110665 | May 1988 | JPX |
0132478 | June 1988 | JPX |
63-132478 | June 1988 | JPX |
1-183844 | July 1989 | JPX |
2-234462 | September 1990 | JPX |
0162771 | June 1992 | JPX |
5-315610 | November 1993 | JPX |
- Patent Abstracts of Japan, vol. 11, No. 108 (E-495) Apr. 4, 1987. Patent Abstracts of Japan, vol. 18, No. 199 (E-1534) Apr. 7, 1994. Patent Abstracts of Japan, vol. 16, No. 521 (E-1285) Oct. 27, 1992. Patent Abstracts of Japan, vol. 009, No. 321 (E-367) Dec. 17, 1985. Patent Abstracts of Japan, vol. 018, No. 120 (E-1516) Feb. 25, 1994. Patent Abstract of Japan, vol. 008, No. 243 (E-277) Nov. 8, 1984. Patent Abstract of Japan, vol. 006, No. 205 (E-136) Oct. 16, 1982.
Type: Grant
Filed: Jul 18, 1995
Date of Patent: May 18, 1999
Assignee: Seiko Instruments Inc.
Inventors: Fumiyasu Utsunomiya (Chiba), Yutaka Saitoh (Chiba), Naoto Saitoh (Chiba), Jun Osanai (Chiba), Haruo Konishi (Chiba), Masanori Miyagi (Chiba)
Primary Examiner: Tom Thomas
Assistant Examiner: David B. Hardy
Law Firm: Adams & Wilks
Application Number: 8/503,828
International Classification: H01L29/772;