Patents by Inventor Naoto Sasaki
Naoto Sasaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240150585Abstract: To further improve, even under OT bending with the use of a Zn—Al—Mg-based alloy plated steel sheet as a base sheet, corrosion resistance regarding corrosion under paint film at a OT bent portion and a periphery thereof, without causing occurrence of cracks and peeling in the paint film. A pre-coated plated steel sheet according to the present invention includes: a plating layer composed of Zn—Al—Mg-based alloy plating, the plating layer being positioned on one side or both sides of a steel sheet; a chemical treatment film layer positioned on the plating layer; and a paint film layer positioned on the chemical treatment film, in which the paint film layer includes a primer paint film layer, and an upper paint film layer positioned on the primer paint film layer, and at least any of the following is satisfied: both a condition (a-1) and a condition (a-2); a condition (b); and a condition (c).Type: ApplicationFiled: March 23, 2022Publication date: May 9, 2024Applicant: NIPPON STEEL CORPORATIONInventors: Hiroyasu FURUKAWA, Takashi FUJII, Fumio SHIBAO, Kohei UEDA, Akira NAKAGAWA, Yuki YAMAMURA, Naoto SASAKI
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Patent number: 11964495Abstract: Provided is an ink set including: an ink containing a cyan pigment; an ink containing a magenta pigment; and an ink containing a yellow pigment, wherein the proportion of the cyan pigment is 0.70% by mass or greater but 1.40% by mass or less, and wherein the proportion of the magenta pigment and the proportion of the yellow pigment are both higher than the proportion of the cyan pigment.Type: GrantFiled: January 21, 2020Date of Patent: April 23, 2024Assignee: Ricoh Company, Ltd.Inventors: Hiromi Sakaguchi, Itsuro Sasaki, Ayaka Tanaka, Naoto Shimura, Shunsuke Horie, Hiroshi Gotou, Yuta Nakamura
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Publication number: 20240103783Abstract: An image processing apparatus includes a processor configured to impose a group of pages on a single sheet as a target for reprinting and perform reprinting, the group of pages being referred to as printing-error pages, each of the pages having been printed with a printing error that occurred while multiple pages imposed on one or more sheets were printed.Type: ApplicationFiled: March 7, 2023Publication date: March 28, 2024Applicant: FUJIFILM BUSINESS INNOVATION CORP.Inventors: Bo LIU, Kimihiko Sasaki, Mari Kodama, Yuka Sugiyama, Yoshie Ohira, Naoto Yamasaki, Kazuki Nagashima
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Publication number: 20240101391Abstract: A system for detecting a presence of a person in a hoistway, having: one or more controllers configured to authenticate the person in the hoistway; the one or more controllers being operationally connected to an elevator car in the hoistway and configured to determine whether the person is within a predetermined distance of the elevator car from a signal emitter on the person; wherein when the person is within the predetermined distance of the elevator car, the one or more controllers is configured to transmit a feedback request to the person and stop the elevator car unless the one or more controllers receives feedback to the feedback request within a predetermined period of time.Type: ApplicationFiled: September 26, 2022Publication date: March 28, 2024Inventors: Jayapal Reddy Gireddy, Helge Krambeck, Xinjin Zheng, Yuzhen Xue, Koji Kiyomoto, Arnaud Blanchard, Daigoro Kurokawa, Kazuya Yamamura, Hideki Arai, Terumitsu Saito, Hideaki Sasaki, Takashi Tanaka, Naoto Furuichi
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Publication number: 20240098209Abstract: A disclosed managing apparatus and image forming apparatus management system ensure confidentiality of information in an image forming apparatus while usability is maintained. An image forming apparatus acquires IC card identifying information with an IC card reader. A management server acquires a user ID associated with the acquired IC card identifying information and use limit information concerning use of the image forming apparatus. A process is performed in the image forming apparatus in accordance with the use limit information.Type: ApplicationFiled: October 30, 2023Publication date: March 21, 2024Applicant: Ricoh Company, Ltd.Inventors: Atsushi SAKAGAMI, Naoto SAKURAI, Koji SASAKI, Daiya MIYASAKA, Tomoko NISHIZAWA, Yasuhiko TSUGAWA, Yohei ONO
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Publication number: 20240078054Abstract: An information processing system includes one or more processors configured to: acquire past printing request information on a printing request received in a past, record information on a record of printing performed by a printer based on the past printing request information, and new printing request information on a newly received printing request; and present a candidate for paper to be used for printing related to the new printing request information based on the past printing request information, information included in the record information and related to paper used for the printing, and an attribute of paper to be used as a print medium. The attribute of paper is identified from the new printing request information.Type: ApplicationFiled: March 14, 2023Publication date: March 7, 2024Applicant: FUJIFILM Business Innovation Corp.Inventors: Yuka SUGIYAMA, Naoto YAMASAKI, Mari KODAMA, Kimihiko SASAKI, Bo LIU
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Publication number: 20240074077Abstract: A press-contact guide, a restraining guide, and a latching mechanism are provided between a housing of a device body and a cover. A restraining projection provided on the cover is inserted into an introduction opening to cause a press-contact projection to be pressed into contact with a press-contact slide part. In this state, the cover is slid in a latching-force-acting direction. Then, the cover moves with a restraining projection being restrained by the restraining guide and cause a projecting latch to latch into a receiving hole. When such a latched state is established, the cover and the housing go out of contact with each other at the press-contact guide and the restraining guide.Type: ApplicationFiled: August 7, 2023Publication date: February 29, 2024Applicant: Alps Alpine Co., Ltd.Inventor: Naoto Sasaki
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Publication number: 20240055451Abstract: The height of a solid-state imaging element is further reduced as compared to the related art. A solid-state imaging element that is a wafer-level chip size package, including: an optical sensor chip; a protective layer that is stacked on a light receiving surface of the optical sensor chip; and a rewiring layer that is stacked on a surface opposite to the light receiving surface of the optical sensor chip, in which a connection terminal of the rewiring layer is a copper flat pad without a solder ball, an alloy layer of tin and copper is not formed on a front surface of the flat pad, and a thermal expansion coefficient of the protective layer is substantially balanced with a thermal expansion coefficient of the rewiring layer.Type: ApplicationFiled: October 4, 2023Publication date: February 15, 2024Inventors: NAOTO SASAKI, YUTAKA OOKA
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Publication number: 20240021498Abstract: A yield is improved in a semiconductor device in which a through electrode covered with an insulating film is formed. A semiconductor device includes a through electrode, an insulating film, and a wiring layer. In a semiconductor device including a through electrode, an insulating film, and a wiring layer, the through electrode penetrates the semiconductor substrate along a direction perpendicular to a predetermined front surface of the semiconductor substrate. Furthermore, the insulating film covers the through electrode. Moreover, the wiring layer includes a dummy gate disposed in a region between an outer periphery of the insulating film and an inner periphery of the insulating film on the front surface.Type: ApplicationFiled: October 14, 2021Publication date: January 18, 2024Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Takushi SHIGETOSHI, Naoto SASAKI, Kenichi SAITOU
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Patent number: 11804502Abstract: The height of a solid-state imaging element is further reduced as compared to the related art. A solid-state imaging element that is a wafer-level chip size package, including: an optical sensor chip; a protective layer that is stacked on a light receiving surface of the optical sensor chip; and a rewiring layer that is stacked on a surface opposite to the light receiving surface of the optical sensor chip, in which a connection terminal of the rewiring layer is a copper flat pad without a solder ball, an alloy layer of tin and copper is not formed on a front surface of the flat pad, and a thermal expansion coefficient of the protective layer is substantially balanced with a thermal expansion coefficient of the rewiring layer.Type: GrantFiled: February 21, 2023Date of Patent: October 31, 2023Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Naoto Sasaki, Yutaka Ooka
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Publication number: 20230197745Abstract: The height of a solid-state imaging element is further reduced as compared to the related art. A solid-state imaging element that is a wafer-level chip size package, including: an optical sensor chip; a protective layer that is stacked on a light receiving surface of the optical sensor chip; and a rewiring layer that is stacked on a surface opposite to the light receiving surface of the optical sensor chip, in which a connection terminal of the rewiring layer is a copper flat pad without a solder ball, an alloy layer of tin and copper is not formed on a front surface of the flat pad, and a thermal expansion coefficient of the protective layer is substantially balanced with a thermal expansion coefficient of the rewiring layer.Type: ApplicationFiled: February 21, 2023Publication date: June 22, 2023Inventors: NAOTO SASAKI, YUTAKA OOKA
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Patent number: 11619772Abstract: The present technology relates to a semiconductor chip and an electronic apparatus that can suppress degradation of optical characteristics of a semiconductor chip including an image pickup device. A semiconductor chip includes: an image pickup device; a transparent protective member that protects the image pickup device; an IR cut film arranged between a light-receiving surface of the image pickup device and the protective member; a bonding layer that bonds the IR cut film and the protective member together; and a protective film that covers side surfaces of the IR cut film and the bonding layer. The present technology can be applied to, for example, a semiconductor chip for an image pickup device.Type: GrantFiled: June 10, 2021Date of Patent: April 4, 2023Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Naoto Sasaki, Yutaka Ooka
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Patent number: 11616090Abstract: The height of a solid-state imaging element is further reduced as compared to the related art. A solid-state imaging element that is a wafer-level chip size package, including: an optical sensor chip; a protective layer that is stacked on a light receiving surface of the optical sensor chip; and a rewiring layer that is stacked on a surface opposite to the light receiving surface of the optical sensor chip, in which a connection terminal of the rewiring layer is a copper flat pad without a solder ball, an alloy layer of tin and copper is not formed on a front surface of the flat pad, and a thermal expansion coefficient of the protective layer is substantially balanced with a thermal expansion coefficient of the rewiring layer.Type: GrantFiled: May 11, 2021Date of Patent: March 28, 2023Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Naoto Sasaki, Yutaka Ooka
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Patent number: 11610929Abstract: The present disclosure relates to a semiconductor element, a manufacturing method of a semiconductor element, and an electronic apparatus, which enable suppression of crack occurrences and leaks. The present technology has a laminated structure including an insulating film having a CTE value between those of metal and Si and disposed under a metal wiring, and P—SiO (1 ?m) having good coverage and disposed as a via inner insulating film in a TSV side wall portion. As the insulating film having a CTE that is in the middle between those of metal and Si, for example, SiOC is used with a thickness of 0.1 ?m and 2 ?m respectively in the via inner insulating film and a field top insulating film continuous to the via inner insulating film. The present disclosure can be applied to, for example, a solid-state imaging element used in an imaging device.Type: GrantFiled: February 12, 2021Date of Patent: March 21, 2023Assignee: SONY CORPORATIONInventor: Naoto Sasaki
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Publication number: 20230056708Abstract: Please replace the currently pending Abstract with the following amended A parasitic capacitance of a wiring arranged on a back surface side of a semiconductor substrate is reduced. A semiconductor apparatus includes a semiconductor substrate, a back surface side wiring, a through wiring, and a separation region. In the semiconductor substrate, a semiconductor element and a front surface side wiring connected to the semiconductor element are arranged on a front surface side. The back surface side wiring is arranged on a back surface side of the semiconductor substrate. The through wiring is arranged in a through hole formed in the semiconductor substrate to connect the front surface side wiring and the back surface side wiring. The separation region is arranged between the semiconductor substrate and the back surface side wiring.Type: ApplicationFiled: February 15, 2021Publication date: February 23, 2023Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Naoto SASAKI, Kenichi SAITOU, Yusuke HAYASHI, Atsuhiko YAMADA, Takushi SHIGETOSHI, Takuya OOI
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Publication number: 20220408560Abstract: An electronic component mounted body includes a substrate, a connection section provided on the substrate, an electronic component having a terminal connected to the connection section, and a solder that fixes the electronic component to the connection section. The connection section has a first region in which the terminal is fixed through the solder, and a second region lower in wettability than the first region, and the second region has an extension region extended to a peripheral edge of the connection section, and a spaced region that projects from the extension region toward the first region and that is provided to be spaced from the peripheral edge.Type: ApplicationFiled: December 1, 2020Publication date: December 22, 2022Applicant: SONY GROUP CORPORATIONInventors: Koji AOYAMA, Naoto SASAKI
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Publication number: 20220157873Abstract: A semiconductor device includes a first semiconductor substrate in which a pixel region where pixel portions performing photoelectric conversion are two-dimensionally arranged is formed and a second semiconductor substrate in which a logic circuit processing a pixel signal output from the pixel portion is formed, the first and second semiconductor substrates being laminated. A protective substrate protecting an on-chip lens is disposed on the on-chip lens in the pixel region of the first semiconductor substrate with a sealing resin interposed therebetween.Type: ApplicationFiled: February 2, 2022Publication date: May 19, 2022Applicant: SONY GROUP CORPORATIONInventors: Naoki KOMAI, Naoto SASAKI, Naoki OGAWA, Takashi OINOUE, Hayato IWAMOTO, Yutaka OOKA, Masaya NAGATA
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Publication number: 20220037272Abstract: A semiconductor device according to the present disclosure includes a board and a via. In the board, a wiring layer is embedded. The via extends in a depth direction from a main surface of the board to pierce through the wiring layer, and is connected to the wiring layer on a side peripheral surface.Type: ApplicationFiled: December 4, 2019Publication date: February 3, 2022Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventor: Naoto SASAKI
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Publication number: 20210302634Abstract: The present technology relates to a semiconductor chip and an electronic apparatus that can suppress degradation of optical characteristics of a semiconductor chip including an image pickup device. A semiconductor chip includes: an image pickup device; a transparent protective member that protects the image pickup device; an IR cut film arranged between a light-receiving surface of the image pickup device and the protective member; a bonding layer that bonds the IR cut film and the protective member together; and a protective film that covers side surfaces of the IR cut film and the bonding layer. The present technology can be applied to, for example, a semiconductor chip for an image pickup device.Type: ApplicationFiled: June 10, 2021Publication date: September 30, 2021Inventors: NAOTO SASAKI, YUTAKA OOKA
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Publication number: 20210265404Abstract: The height of a solid-state imaging element is further reduced as compared to the related art. A solid-state imaging element that is a wafer-level chip size package, including: an optical sensor chip; a protective layer that is stacked on a light receiving surface of the optical sensor chip; and a rewiring layer that is stacked on a surface opposite to the light receiving surface of the optical sensor chip, in which a connection terminal of the rewiring layer is a copper flat pad without a solder ball, an alloy layer of tin and copper is not formed on a front surface of the flat pad, and a thermal expansion coefficient of the protective layer is substantially balanced with a thermal expansion coefficient of the rewiring layer.Type: ApplicationFiled: May 11, 2021Publication date: August 26, 2021Inventors: NAOTO SASAKI, YUTAKA OOKA