Patents by Inventor Naoya Furutake
Naoya Furutake has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170309336Abstract: A semiconductor storage device including a plurality of memory cells, each including a variable resistance element, and control circuitry that executes a first writing process of applying a first writing pulse to a memory cell to turn the memory cell state into a first resistance state and a second writing process of applying a second writing pulse of opposite polarity to the first writing pulse to turn the memory cell into a second resistance state, the memory cell from among the plurality of memory cells. The control circuitry, when the memory cell is placed in the second resistance state, after applying the first writing pulse to the memory cell, applies a reading pulse for a verify process of reading whether the variable resistance element is placed in the first resistance state or the second resistance state.Type: ApplicationFiled: July 11, 2017Publication date: October 26, 2017Inventors: Takashi HASE, Naoya FURUTAKE, Koji MASUZAKI
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Patent number: 9711216Abstract: When writing ReRAM cells, it is pursued to set the cells in a sufficiently high or low resistance state, while preventing excessive writing. Disclosed is a semiconductor storage device including memory cells, each including a variable resistance element, and control circuitry that executes an Off writing process of applying Off writing pulse to a memory cell to turn it into high resistance state and an On writing process of applying On writing pulse to turn it into low resistance state. The control circuitry, when the memory cell is placed in low resistance state, after applying Off writing pulse, applies a reading pulse for a verify process of reading whether it is placed in high or low resistance state. If the memory cell is not placed in high resistance state as a result of the verify process, the control circuitry applies a reset pulse comprising On writing pulse, applies Off writing pulse with extended pulse width and executes the verify process in mentioned order.Type: GrantFiled: December 8, 2015Date of Patent: July 18, 2017Assignee: Renesas Electronics CorporationInventors: Takashi Hase, Naoya Furutake, Koji Masuzaki
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Publication number: 20160276026Abstract: When writing ReRAM cells, it is pursued to set the cells in a sufficiently high or low resistance state, while preventing excessive writing. Disclosed is a semiconductor storage device including memory cells, each including a variable resistance element, and control circuitry that executes an Off writing process of applying Off writing pulse to a memory cell to turn it into high resistance state and an On writing process of applying On writing pulse to turn it into low resistance state. The control circuitry, when the memory cell is placed in low resistance state, after applying Off writing pulse, applies a reading pulse for a verify process of reading whether it is placed in high or low resistance state. If the memory cell is not placed in high resistance state as a result of the verify process, the control circuitry applies a reset pulse comprising On writing pulse, applies Off writing pulse with extended pulse width and executes the verify process in mentioned order.Type: ApplicationFiled: December 8, 2015Publication date: September 22, 2016Inventors: Takashi HASE, Naoya FURUTAKE, Koji MASUZAKI
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Publication number: 20160240564Abstract: A semiconductor device has a p-type metal oxide semiconductor layer; a source electrode connected with the p-type metal oxide semiconductor layer; a drain electrode connected with the p-type metal oxide semiconductor layer; and a gate electrode arranged to oppose to a part of the p-type metal oxide semiconductor layer. The gate electrode and the drain electrode are separated from each other in a top view.Type: ApplicationFiled: April 27, 2016Publication date: August 18, 2016Inventors: Hiroshi SUNAMURA, Kishou KANEKO, Naoya FURUTAKE, Shinobu SAITOU, Yoshihiro HAYASHI
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Patent number: 9356026Abstract: A semiconductor device has a p-type metal oxide semiconductor layer; a source electrode connected with the p-type metal oxide semiconductor layer; a drain electrode connected with the p-type metal oxide semiconductor layer; and a gate electrode arranged to oppose to a part of the p-type metal oxide semiconductor layer. The gate electrode and the drain electrode are separated from each other in a top view.Type: GrantFiled: October 6, 2015Date of Patent: May 31, 2016Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Hiroshi Sunamura, Kishou Kaneko, Naoya Furutake, Shinobu Saitou, Yoshihiro Hayashi
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Publication number: 20160148845Abstract: A semiconductor device is provided which includes an N-type semiconductor layer and a P-type semiconductor layer coexisting in the same wiring layer without influences on the properties of a semiconductor layer. The semiconductor device includes a first wiring layer with a first wiring, a second wiring layer with a second wiring, and first and second transistors provided in the first and second wiring layers. The first transistor includes a first gate electrode, a first gate insulating film, a first oxide semiconductor layer, a first hard mask layer, and first insulating sidewall films covering the sides of the first oxide semiconductor layer. The second transistor includes a second gate electrode, a second gate insulating film, a second oxide semiconductor layer, and a second hard mask layer.Type: ApplicationFiled: November 24, 2015Publication date: May 26, 2016Inventors: Hiroshi Sunamura, Kishou Kaneko, Naoya Furutake, Shinobu Saitou, Yoshihiro Hayashi
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Patent number: 9257390Abstract: A semiconductor device includes a semiconductor substrate, an insulating film formed above the semiconductor substrate, and a multilayered wiring formed in a prescribed area within the insulating film. The multilayered wiring includes a dual damascene wiring positioned on at least one layer of the multilayered wiring. The dual damascene wiring includes an alloy having copper as a principal component. A concentration of at least one metallic element contained as an added component of the alloy in a via connected to the dual damascene wiring is 10% or more higher in a via connected to a wiring whose width exceeds by five or more times a diameter of the via than that in another via connected to another wiring of a smallest width in a same upper wiring layer of the multilayered wiring.Type: GrantFiled: November 24, 2014Date of Patent: February 9, 2016Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Mari Amano, Munehiro Tada, Naoya Furutake, Yoshihiro Hayashi
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Publication number: 20160027925Abstract: A semiconductor device has a p-type metal oxide semiconductor layer; a source electrode connected with the p-type metal oxide semiconductor layer; a drain electrode connected with the p-type metal oxide semiconductor layer; and a gate electrode arranged to oppose to a part of the p-type metal oxide semiconductor layer. The gate electrode and the drain electrode are separated from each other in a top view.Type: ApplicationFiled: October 6, 2015Publication date: January 28, 2016Inventors: Hiroshi SUNAMURA, Kishou KANEKO, Naoya FURUTAKE, Shinobu SAITOU, Yoshihiro HAYASHI
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Patent number: 9230865Abstract: A semiconductor device is provided which includes an N-type semiconductor layer and a P-type semiconductor layer coexisting in the same wiring layer without influences on the properties of a semiconductor layer. The semiconductor device includes a first wiring layer with a first wiring, a second wiring layer with a second wiring, and first and second transistors provided in the first and second wiring layers. The first transistor includes a first gate electrode, a first gate insulating film, a first oxide semiconductor layer, a first hard mask layer, and first insulating sidewall films covering the sides of the first oxide semiconductor layer. The second transistor includes a second gate electrode, a second gate insulating film, a second oxide semiconductor layer, and a second hard mask layer.Type: GrantFiled: May 12, 2015Date of Patent: January 5, 2016Assignee: Renesas Electronics CorporationInventors: Hiroshi Sunamura, Kishou Kaneko, Naoya Furutake, Shinobu Saitou, Yoshihiro Hayashi
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Patent number: 9190475Abstract: A semiconductor device has a p-type metal oxide semiconductor layer; a source electrode connected with the p-type metal oxide semiconductor layer; a drain electrode connected with the p-type metal oxide semiconductor layer; and a gate electrode arranged to oppose to a part of the p-type metal oxide semiconductor layer. The gate electrode and the drain electrode are separated from each other in a top view.Type: GrantFiled: September 13, 2013Date of Patent: November 17, 2015Assignee: Renesas Electronics CorporationInventors: Hiroshi Sunamura, Kishou Kaneko, Naoya Furutake, Shinobu Saitou, Yoshihiro Hayashi
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Publication number: 20150243562Abstract: A semiconductor device is provided which includes an N-type semiconductor layer and a P-type semiconductor layer coexisting in the same wiring layer without influences on the properties of a semiconductor layer. The semiconductor device includes a first wiring layer with a first wiring, a second wiring layer with a second wiring, and first and second transistors provided in the first and second wiring layers. The first transistor includes a first gate electrode, a first gate insulating film, a first oxide semiconductor layer, a first hard mask layer, and first insulating sidewall films covering the sides of the first oxide semiconductor layer. The second transistor includes a second gate electrode, a second gate insulating film, a second oxide semiconductor layer, and a second hard mask layer.Type: ApplicationFiled: May 12, 2015Publication date: August 27, 2015Inventors: Hiroshi Sunamura, Kishou Kaneko, Naoya Furutake, Shinobu Saitou, Yoshihiro Hayashi
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Patent number: 9082643Abstract: A semiconductor device is provided which includes an N-type semiconductor layer and a P-type semiconductor layer coexisting in the same wiring layer without influences on the properties of a semiconductor layer. The semiconductor device includes a first wiring layer with a first wiring, a second wiring layer with a second wiring, and first and second transistors provided in the first and second wiring layers. The first transistor includes a first gate electrode, a first gate insulating film, a first oxide semiconductor layer, a first hard mask layer, and first insulating sidewall films covering the sides of the first oxide semiconductor layer. The second transistor includes a second gate electrode, a second gate insulating film, a second oxide semiconductor layer, and a second hard mask layer.Type: GrantFiled: August 21, 2013Date of Patent: July 14, 2015Assignee: Renesas Electronics CorporationInventors: Hiroshi Sunamura, Kishou Kaneko, Naoya Furutake, Shinobu Saitou, Yoshihiro Hayashi
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Publication number: 20150102492Abstract: A semiconductor device includes a semiconductor substrate, an insulating film formed above the semiconductor substrate, and a multilayered wiring formed in a prescribed area within the insulating film. The multilayered wiring includes a dual damascene wiring positioned on at least one layer of the multilayered wiring. The dual damascene wiring includes an alloy having copper as a principal component. A concentration of at least one metallic element contained as an added component of the alloy in a via connected to the dual damascene wiring is 10% or more higher in a via connected to a wiring whose width exceeds by five or more times a diameter of the via than that in another via connected to another wiring of a smallest width in a same upper wiring layer of the multilayered wiring.Type: ApplicationFiled: November 24, 2014Publication date: April 16, 2015Inventors: Mari Amano, Munehiro Tada, Naoya Furutake, Yoshihiro Hayashi
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Patent number: 8916466Abstract: A semiconductor device includes a semiconductor substrate, an insulating film formed above the semiconductor substrate, and a multilayered wiring formed in a prescribed area within the insulating film. The multilayered wiring includes a dual damascene wiring positioned on at least one layer of the multilayered wiring. The dual damascene wiring includes an alloy having copper as a principal component. A concentration of at least one metallic element contained as an added component of the alloy in a via connected to the dual damascene wiring is 10% or more higher in a via connected to a wiring whose width exceeds by five or more times a diameter of the via than that in another via connected to another wiring of a smallest width in a same upper wiring layer of the multilayered wiring.Type: GrantFiled: July 11, 2011Date of Patent: December 23, 2014Assignee: Renesas Electronics CorporationInventors: Mari Amano, Munehiro Tada, Naoya Furutake, Yoshihiro Hayashi
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Publication number: 20140357047Abstract: A semiconductor device includes a first insulating layer (interlayer insulating layer), a resistive element that is disposed over the first insulating layer (interlayer insulating layer) and at least a surface layer of which is a TaSiN layer, and an interlayer insulating layer disposed over the first insulating layer (interlayer insulating layer) and the resistive element. Multiple via plugs having ends coupled to the TaSiN layer are disposed in the interlayer insulating layer.Type: ApplicationFiled: August 13, 2014Publication date: December 4, 2014Inventors: Jun KAWAHARA, Naoya INOUE, Naoya FURUTAKE, Yoshihiro HAYASHI
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Patent number: 8829649Abstract: A semiconductor device includes a first insulating layer (interlayer insulating layer), a resistive element that is disposed over the first insulating layer (interlayer insulating layer) and at least a surface layer of which is a TaSiN layer, and an interlayer insulating layer disposed over the first insulating layer (interlayer insulating layer) and the resistive element. Multiple via plugs having ends coupled to the TaSiN layer are disposed in the interlayer insulating layer.Type: GrantFiled: November 6, 2012Date of Patent: September 9, 2014Assignee: Renesas Electronics CorporationInventors: Jun Kawahara, Naoya Inoue, Naoya Furutake, Yoshihiro Hayashi
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Patent number: 8759212Abstract: A method of manufacturing a semiconductor device includes: forming a cap insulating film, including Si and C, on a substrate; forming an organic silica film, having a composition ratio of the number of carbon atoms to the number of silicon atoms higher than that of the cap insulating film, on the cap insulating film; and forming two or more concave portions, having different opening diameters, in the organic silica film, by plasma processing in which mixed gas including inert gas, N-containing gas, fluorocarbon gas and oxidant gas is used.Type: GrantFiled: May 5, 2011Date of Patent: June 24, 2014Assignee: Renesas Electronics CorporationInventors: Ippei Kume, Jun Kawahara, Naoya Furutake, Shinobu Saitou, Yoshihiro Hayashi
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Patent number: 8715791Abstract: A method for forming porous insulating film using cyclic siloxane raw material monomer, includes forming porous insulating film using the mixed gas of a cyclic organosiloxane raw material and a compound raw material including a part of chemical structure including the cyclic organosiloxane raw material. The compound raw material may include a compound including a part of side chain of the cyclic organosiloxane raw material.Type: GrantFiled: September 8, 2006Date of Patent: May 6, 2014Assignee: Renesas Electronics CorporationInventors: Munehiro Tada, Naoya Furutake, Tsuneo Takeuchi, Yoshihiro Hayashi
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Publication number: 20140077206Abstract: A semiconductor device has a p-type metal oxide semiconductor layer; a source electrode connected with the p-type metal oxide semiconductor layer; a drain electrode connected with the p-type metal oxide semiconductor layer; and a gate electrode arranged to oppose to a part of the p-type metal oxide semiconductor layer. The gate electrode and the drain electrode are separated from each other in a top view.Type: ApplicationFiled: September 13, 2013Publication date: March 20, 2014Applicant: Renesas Electronics CorporationInventors: Hiroshi Sunamura, Kishou Kaneko, Naoya Furutake, Shinobu Saitou, Yoshihiro Hayashi
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Publication number: 20140054584Abstract: A semiconductor device is provided which includes an N-type semiconductor layer and a P-type semiconductor layer coexisting in the same wiring layer without influences on the properties of a semiconductor layer. The semiconductor device includes a first wiring layer with a first wiring, a second wiring layer with a second wiring, and first and second transistors provided in the first and second wiring layers. The first transistor includes a first gate electrode, a first gate insulating film, a first oxide semiconductor layer, a first hard mask layer, and first insulating sidewall films covering the sides of the first oxide semiconductor layer. The second transistor includes a second gate electrode, a second gate insulating film, a second oxide semiconductor layer, and a second hard mask layer.Type: ApplicationFiled: August 21, 2013Publication date: February 27, 2014Applicant: Renesas Electronics CorporationInventors: Hiroshi Sunamura, Kishou Kaneko, Naoya Furutake, Shinobu Saitou, Yoshihiro Hayashi