Patents by Inventor Naoya Kobayashi

Naoya Kobayashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5113392
    Abstract: In a network having a plurality of node apparatus connected to a transmission line, each node apparatus segmenting a transmission message into information blocks of a predetermined length and transmitting them to the transmission line in the form of a fixed length packet (cell) having a source address, each node apparatus sequentially stores packets having different source addresses in vacant memory blocks of a buffer memory. There is written in each memory block the packet data as well as a next address pointer indicating a memory block in which the next received packet having the same source address is stored. When a packet containing the last information block of a message is received, stored in a read address queue is the address indicating the memory block which stores the first information block of the same packet.
    Type: Grant
    Filed: June 18, 1990
    Date of Patent: May 12, 1992
    Assignees: Hitachi, Ltd., Hitachi Microcomputer Engineering Ltd.
    Inventors: Yoshihiro Takiyasu, Mitsuhiro Yamaga, Kazunori Nakamura, Eiichi Amada, Hidehiko Jusa, Naoya Kobayashi, Osamu Takada, Satoru Hirayama, Tatsuhito Iiyama
  • Patent number: 5042027
    Abstract: A communication network system includes a communication line, a plurality of communication stations each having a node coupled to the communication line and a network controller coupled to the stations for controlling routing for communication messages between nodes. In one embodiment, the messages are sent from plural terminals connected with each node along with communication performance prerequisites. The communication performance prerequisites for a communication message are discriminated in the node which receives the message. Traffic in various routes between the nodes is continually measured in the communication stations and the measuring results are stored in a database storage unit.
    Type: Grant
    Filed: September 8, 1989
    Date of Patent: August 20, 1991
    Assignee: Hitachi, Ltd.
    Inventors: Akihiko Takase, Masahiro Takatori, Yoshiaki Takemura, Naoya Kobayashi, Yasushi Sawada, Yukio Nakano, Yasushi Takahashi, Masahiro Koya, Yoshitaka Takasaki
  • Patent number: 4926499
    Abstract: A simplified carrier phase control apparatus used in a modem for demodulating a quadrature amplitude modulated data signal, to correct phase jitters of a carrier signal due to a 50 Hz or a 60 Hz frequency of the commercial power supply, and its harmonic wave frequency components. The carrier phase control apparatus has a predictive filter for predicting a carrier phase jitter, the predictive filter composed of band-pass filters with center frequencies of 50 Hz and 60 Hz, and a circuit where the output signals of the band-pass filters are multiplied by the coefficients and added linearly.
    Type: Grant
    Filed: November 18, 1987
    Date of Patent: May 15, 1990
    Assignee: Hitachi, Ltd.
    Inventors: Naoya Kobayashi, Makoto Ohnishi, Yoshiro Kokuryo
  • Patent number: 4823346
    Abstract: A maximum likelihood decoder for decoding a code from a signal transmitted through quadrature amplitude modulation of a code including a convolutional code can decode at high speed and high accuracy with a simple hardware configuration. In the maximum likelihood decoding of the convolutional code, the metric processing is not carried out for all of the possible paths and states but a smaller number of path(s) (metric(s)) and state(s) (metric(s)) are selected in a descending order to determine survival paths.
    Type: Grant
    Filed: April 16, 1987
    Date of Patent: April 18, 1989
    Assignees: Hitachi, Ltd., Hitachi Denshi Kabushiki
    Inventors: Naoya Kobayashi, Makoto Ohnishi, Yoshiro Kokuryo