Patents by Inventor Naoya Mashiko

Naoya Mashiko has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070239916
    Abstract: Input-output devices are prevented from conducting false output due to faulty operation by providing an input-output control apparatus configured to store input-output values to be used by a processor to conduct arithmetic operation in a mode having a relatively high safety requirement, in a first storage area, store input-output values to be used by the processor to conduct arithmetic operation in a mode having a relatively low safety requirement, in a second storage area, and restrict copying to the first storage area, copying from the first storage area, copying to the second storage area, or copying from the second storage area according to the mode concerning the safety requirement.
    Type: Application
    Filed: June 30, 2006
    Publication date: October 11, 2007
    Inventors: Naoya Mashiko, Takashi Umehara, Masamitsu Kobayashi, Hiromichi Endoh, Akihiro Onozuka, Akira Bando, Shin Kokura, Hisao Nagayama, Masakazu Ishikawa, Satoru Funaki, Masahiro Shiraishi
  • Publication number: 20070055480
    Abstract: A self-diagnosis system of a processor capable of realizing a sufficiently high processing ability for control tasks is provided without deteriorating reliability of safety controls even in complex diagnostic techniques. The self-diagnosis system is equipped with a diagnostic target area allocator for allocating a non-active area within a memory as a diagnosis-ready area, which is not used in a control task under execution by a main processor in an independent manner from the main processor; and a diagnostic executor for executing a diagnosis based upon a predetermined sequence in an independent manner from the main processor. In the self-diagnosis system, a diagnostic target area segmented from the diagnosis-ready area is selected, and a diagnosis of the selected diagnostic target area is carried out in each of diagnostic cycles by the diagnostic executor.
    Type: Application
    Filed: September 1, 2006
    Publication date: March 8, 2007
    Inventors: Hiromichi Endoh, Tsutomu Yamada, Naoya Mashiko, Takashi Umehara
  • Publication number: 20070006025
    Abstract: The system has, provided in a sending device, a generator generating transmission data including data, a data error detection code generated from the data and a safety flag indicating a degree of reliability, and transmission data; has, provided in a receiving device, a plurality of components of extracting transmission data, a safety flag, and a data error detection code from a received frame, and detecting a data error, a comparator comparing the matching of a plurality of received frames, and a selector selecting one received frame, from the frame error detection result, the safety flag, the data error detection result, and the matching comparison result; and determines the validity of transmitted data by the detection corresponding to the degree of reliability set with the safety flag.
    Type: Application
    Filed: June 30, 2006
    Publication date: January 4, 2007
    Inventors: Akihiro Onozuka, Masakazu Ishikawa, Masamitsu Kobayashi, Takashi Umehara, Shin Kokura, Hiromichi Endoh, Satoru Funaki, Hisao Nagayama, Masahiro Shiraishi, Akira Bando, Eiji Kobayashi, Yasuyuki Furuta, Naoya Mashiko
  • Publication number: 20060282702
    Abstract: Processed results are received when processors make compatible computations on data of a common object. A computation command signal is generated and fed to the processors in response to a start signal from any one of the processors so that the processors can make computations with different operation timings. Then, the results of the computations made by the processors are compared with each other. Thus, apparatus capable of small size, high performance and safety at the same time can be achieved by the above construction using the processors.
    Type: Application
    Filed: June 7, 2006
    Publication date: December 14, 2006
    Inventors: Akira Bando, Shin Kokura, Takashi Umehara, Masamitsu Kobayashi, Hisao Nagayama, Naoya Mashiko, Masahiro Shiraishi, Masakazu Ishikawa, Akihiro Onozuka, Hiromichi Endoh, Tsutomu Yamada, Satoru Funaki