Abstract: In a digital broadcast receiving apparatus for amplifying a received modulated digital signal wave RF with automatically adjusted gain and demodulating the modulated signal wave to a digital signal SDMD, a tuner 2 frequency-converts the modulated digital signal wave Srf to generate a first modulated signal SMA. A first automatic gain control amplification unit AGC1 controls gain of the tuner 2 to make a level of the first modulated signal SMA at a first predetermined level. An A/D converter 3 converts the first modulated signal SMA into a second modulated signal SMD. A demodulator 7 demodulates the second modulated signal SMD to generate a first demodulated digital signal SDD. A second automatic gain control amplifier AGC2a generates a second demodulated digital signal SMDa where frequency fluctuations included in the digital modulated wave Srf are eliminated.

Abstract: A digital demodulation apparatus is provided for automatically controlling gain based on a state of receiving a digital modulated signal.

Abstract: In an automatic gain control amplifier AGCa, an RF automatic gain controller 2 controls the gain of a radio frequency signal Srf. A frequency converter 3, 4 frequency-converts the radio frequency signal Srfa into an intermediate frequency signal Sifa. An IF automatic gain controller 5 controls the gain of the intermediate frequency Sifa. A level detector LDa detects a signal level of the gain-controlled intermediate frequency signal Sifa, and generates a level signal SLa. An automatic gain control signal generator SGa, SGb separately controls, based the level signal SLa, SLb, the RF automatic gain controller 2 and the IF automatic gain controller 5.

Abstract: A memory interface device of the present invention includes: an input buffer including a plurality of input areas; an output buffer including a plurality of output areas; and a control section for controlling the input buffer, the output buffer and a single port memory. The control section controls the input buffer and the single port memory so as to transfer a signal stored in one of the input areas of the input buffer to the single port memory while storing an input signal in another one of the input areas of the input buffer. The control section controls the output buffer and the single part memory so as to output as an output signal a signal stored in one of the output areas of the output buffer while transferring a signal stored in the single port memory to another one of the output areas of the output buffer.

Abstract: A method for loading of program data with high speed and efficiency along with eliminating the need for software modification even if changes occur in the storage addresses and data length of the program data stored in the program memory. In order to load program data in a rewritable manner into a number of functional circuits FC0, FC1, . . . , FCn operating in accordance with the supplied program data, a program memory, for example, a ROM 10, a program loader 12, and program designating apparatus, for example, a microprocessor 14, are provided in the system.