Patents by Inventor Naozumi Morino
Naozumi Morino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10418325Abstract: A metal wiring layer includes a plurality of hierarchical blocks each divided by a side that serves as a boundary. One of the hierarchical blocks is placed to extend along the outer periphery of the self hierarchical block, and includes: a shield ring wire formed by a single metal wire or by a plurality of metal wires; and a plurality of metal wires that are placed inside the shield ring wire and extend in a preferential direction determined in advance. The shield ring wire has a first section extending in the preferential direction and a second section extending in a non-preferential direction perpendicular to the preferential direction.Type: GrantFiled: January 4, 2017Date of Patent: September 17, 2019Assignee: Renesas Electronics CorporationInventors: Hiroki Nishida, Naozumi Morino, Toshimi Mizutani
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Publication number: 20170263550Abstract: A metal wiring layer includes a plurality of hierarchical blocks each divided by a side that serves as a boundary. One of the hierarchical blocks is placed to extend along the outer periphery of the self hierarchical block, and includes: a shield ring wire formed by a single metal wire or by a plurality of metal wires; and a plurality of metal wires that are placed inside the shield ring wire and extend in a preferential direction determined in advance. The shield ring wire has a first section extending in the preferential direction and a second section extending in a non-preferential direction perpendicular to the preferential direction.Type: ApplicationFiled: January 4, 2017Publication date: September 14, 2017Inventors: Hiroki NISHIDA, Naozumi MORINO, Toshimi MIZUTANI
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Patent number: 9515019Abstract: The present invention has for its purpose to provide a technique capable of reducing planar dimension of the semiconductor device. An input/output circuit is formed over the semiconductor substrate, a grounding wiring and a power supply wiring pass over the input/output circuit, and a conductive layer for a bonding pad is formed thereover. The input/output circuit is formed of MISFET elements in the nMISFET forming region and the pMISFET forming region, resistance elements in the resistance element forming regions and diode elements in the diode element forming regions functioning as protective elements. A wiring connected to the protective elements and positioned under the grounding wiring and the power supply wiring is pulled out in a pulling-out region between the nMISFET forming region and the pMISFET forming region and between the grounding wiring and the power supply wiring to be connected to the conductive layer.Type: GrantFiled: April 14, 2016Date of Patent: December 6, 2016Assignee: Renesas Electronics CorporationInventors: Takahiro Hayashi, Shunsuke Toyoshima, Kazuo Sakamoto, Naozumi Morino, Kazuo Tanaka
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Publication number: 20160233154Abstract: The present invention has for its purpose to provide a technique capable of reducing planar dimension of the semiconductor device. An input/output circuit is formed over the semiconductor substrate, a grounding wiring and a power supply wiring pass over the input/output circuit, and a conductive layer for a bonding pad is formed thereover. The input/output circuit is formed of MISFET elements in the nMISFET forming region and the pMISFET forming region, resistance elements in the resistance element forming regions and diode elements in the diode element forming regions functioning as protective elements. A wiring connected to the protective elements and positioned under the grounding wiring and the power supply wiring is pulled out in a pulling-out region between the nMISFET forming region and the pMISFET forming region and between the grounding wiring and the power supply wiring to be connected to the conductive layer.Type: ApplicationFiled: April 14, 2016Publication date: August 11, 2016Inventors: Takahiro Hayashi, Shunsuke Toyoshima, Kazuo Sakamoto, Naozumi Morino, Kazuo Tanaka
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Patent number: 9379100Abstract: A semiconductor integrated circuit device comprises I/O cells arranged around a core region. Each of the I/O cells comprises a level shifter circuit, an I/O logic circuit, and an I/O buffer circuit. An I/O logic region in which the I/O logic circuit is arranged and an I/O buffer region in which the I/O buffer circuit is arranged overlap with a region in which a pad for the I/O cell is arranged. The I/O logic region and the I/O buffer region are arranged side by side in a direction parallel to a side of the core region.Type: GrantFiled: November 28, 2015Date of Patent: June 28, 2016Assignee: Renesas Electronics CorporationInventors: Kazuo Sakamoto, Naozumi Morino, Kazuo Tanaka, Hiroyasu Ishizuka
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Patent number: 9343460Abstract: The present invention has for its purpose to provide a technique capable of reducing planar dimension of the semiconductor device. An input/output circuit is formed over the semiconductor substrate, a grounding wiring and a power supply wiring pass over the input/output circuit, and a conductive layer for a bonding pad is formed thereover. The input/output circuit is formed of MISFET elements in the nMISFET forming region and the pMISFET forming region, resistance elements in the resistance element forming regions and diode elements in the diode element forming regions functioning as protective elements. A wiring connected to the protective elements and positioned under the grounding wiring and the power supply wiring is pulled out in a pulling-out region between the nMISFET forming region and the pMISFET forming region and between the grounding wiring and the power supply wiring to be connected to the conductive layer.Type: GrantFiled: June 22, 2015Date of Patent: May 17, 2016Assignee: Renesas Electronics CorporationInventors: Takahiro Hayashi, Shunsuke Toyoshima, Kazuo Sakamoto, Naozumi Morino, Kazuo Tanaka
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Publication number: 20160079231Abstract: A semiconductor integrated circuit device comprises I/O cells arranged around a core region. Each of the I/O cells comprises a level shifter circuit, an I/O logic circuit, and an I/O buffer circuit. An I/O logic region in which the I/O logic circuit is arranged and an I/O buffer region in which the I/O buffer circuit is arranged overlap with a region in which a pad for the I/O cell is arranged. The I/O logic region and the I/O buffer region are arranged side by side in a direction parallel to a side of the core region.Type: ApplicationFiled: November 28, 2015Publication date: March 17, 2016Inventors: Kazuo Sakamoto, Naozumi Morino, Kazuo Tanaka, Hiroyasu Ishizuka
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Publication number: 20160027731Abstract: A semiconductor device includes a substrate including a circuit region where a circuit element is formed, a multilayer wiring layer that is formed on the substrate and composed of a plurality of wiring layers and a plurality of via layers that are laminated, and an electrode pad that is formed on the multilayer wiring layer. An interlayer insulating film is formed in a region of a first wiring layer that is a top layer of the plurality of wiring layers, in the region the electrode pad and the first circuit region overlapping each other in a planar view of the electrode pad.Type: ApplicationFiled: October 5, 2015Publication date: January 28, 2016Inventors: Ryo Mori, Kazuki Fukuoka, Naozumi Morino, Yoshinori Deguchi
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Patent number: 9209811Abstract: A semiconductor integrated circuit device comprises I/O cells arranged around a core region. Each of the I/O cells comprises a level shifter circuit, an I/O logic circuit, and an I/O buffer circuit. An I/O logic region in which the I/O logic circuit is arranged and an I/O buffer region in which the I/O buffer circuit is arranged overlap with a region in which a pad for the I/O cell is arranged. The I/O logic region and the I/O buffer region are arranged side by side in a direction parallel to a side of the core region.Type: GrantFiled: August 15, 2014Date of Patent: December 8, 2015Assignee: Renesas Electronics CorporationInventors: Kazuo Sakamoto, Naozumi Morino, Kazuo Tanaka, Hiroyasu Ishizuka
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Patent number: 9171767Abstract: A semiconductor device includes a substrate including a circuit region where a circuit element is formed, a multilayer wiring layer that is formed on the substrate and composed of a plurality of wiring layers and a plurality of via layers that are laminated, and an electrode pad that is formed on the multilayer wiring layer. An interlayer insulating film is formed in a region of a first wiring layer that is a top layer of the plurality of wiring layers, in the region the electrode pad and the first circuit region overlapping each other in a planar view of the electrode pad.Type: GrantFiled: November 8, 2014Date of Patent: October 27, 2015Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Ryo Mori, Kazuki Fukuoka, Naozumi Morino, Yoshinori Deguchi
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Publication number: 20150287724Abstract: The present invention has for its purpose to provide a technique capable of reducing planar dimension of the semiconductor device. An input/output circuit is formed over the semiconductor substrate, a grounding wiring and a power supply wiring pass over the input/output circuit, and a conductive layer for a bonding pad is formed thereover. The input/output circuit is formed of MISFET elements in the nMISFET forming region and the pMISFET forming region, resistance elements in the resistance element forming regions and diode elements in the diode element forming regions functioning as protective elements. A wiring connected to the protective elements and positioned under the grounding wiring and the power supply wiring is pulled out in a pulling-out region between the nMISFET forming region and the pMISFET forming region and between the grounding wiring and the power supply wiring to be connected to the conductive layer.Type: ApplicationFiled: June 22, 2015Publication date: October 8, 2015Inventors: Takahiro Hayashi, Shunsuke Toyoshima, Kazuo Sakamoto, Naozumi Morino, Kazuo Tanaka
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Patent number: 9093283Abstract: The present invention has for its purpose to provide a technique capable of reducing planar dimension of the semiconductor device. An input/output circuit is formed over the semiconductor substrate, a grounding wiring and a power supply wiring pass over the input/output circuit, and a conductive layer for a bonding pad is formed thereover. The input/output circuit is formed of MISFET elements in the nMISFET forming region and the pMISFET forming region, resistance elements in the resistance element forming regions and diode elements in the diode element forming regions functioning as protective elements. A wiring connected to the protective elements and positioned under the grounding wiring and the power supply wiring is pulled out in a pulling-out region between the nMISFET forming region and the pMISFET forming region and between the grounding wiring and the power supply wiring to be connected to the conductive layer.Type: GrantFiled: January 7, 2015Date of Patent: July 28, 2015Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Takahiro Hayashi, Shunsuke Toyoshima, Kazuo Sakamoto, Naozumi Morino, Kazuo Tanaka
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Publication number: 20150108579Abstract: The present invention has for its purpose to provide a technique capable of reducing planar dimension of the semiconductor device. An input/output circuit is formed over the semiconductor substrate, a grounding wiring and a power supply wiring pass over the input/output circuit, and a conductive layer for a bonding pad is formed thereover. The input/output circuit is formed of MISFET elements in the nMISFET forming region and the pMISFET forming region, resistance elements in the resistance element forming regions and diode elements in the diode element forming regions functioning as protective elements. A wiring connected to the protective elements and positioned under the grounding wiring and the power supply wiring is pulled out in a pulling-out region between the nMISFET forming region and the pMISFET forming region and between the grounding wiring and the power supply wiring to be connected to the conductive layer.Type: ApplicationFiled: January 7, 2015Publication date: April 23, 2015Inventors: Takahiro Hayashi, Shunsuke Toyoshima, Kazuo Sakamoto, Naozumi Morino, Kazuo Tanaka
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Publication number: 20150076709Abstract: A semiconductor device includes a substrate including a circuit region where a circuit element is formed, a multilayer wiring layer that is formed on the substrate and composed of a plurality of wiring layers and a plurality of via layers that are laminated, and an electrode pad that is formed on the multilayer wiring layer. An interlayer insulating film is formed in a region of a first wiring layer that is a top layer of the plurality of wiring layers, in the region the electrode pad and the first circuit region overlapping each other in a planar view of the electrode pad.Type: ApplicationFiled: November 8, 2014Publication date: March 19, 2015Inventors: Ryo Mori, Kazuki Fukuoka, Naozumi Morino, Yoshinori Deguchi
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Patent number: 8975120Abstract: The reliability of a semiconductor device is to be improved. A microcomputer chip (semiconductor chip) having a plurality of pads formed on a main surface thereof is mounted over an upper surface of a wiring substrate in an opposed state of the chip main surface to the substrate upper surface. Pads coupled to a plurality of terminals (bonding leads) formed over the substrate upper surface comprise a plurality of first pads in which a unique electric current different from the electric current flowing through other pads flows and a plurality of second pads in which an electric current common to the pads flows or does not flow. Another first pad of the first pads or one of the second pads are arranged next to the first pad. The first pads are electrically coupled to a plurality of bonding leads respectively via a plurality of bumps (first conductive members), while the second pads are bonded to the terminals via a plurality of bumps (second conductive members).Type: GrantFiled: March 11, 2014Date of Patent: March 10, 2015Assignee: Renesas Electronics CorporationInventors: Naoto Taoka, Atsushi Nakamura, Naozumi Morino, Toshikazu Ishikawa, Nobuhiro Kinoshita
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Patent number: 8946770Abstract: The present invention has for its purpose to provide a technique capable of reducing planar dimension of the semiconductor device. An input/output circuit is formed over the semiconductor substrate, a grounding wiring and a power supply wiring pass over the input/output circuit, and a conductive layer for a bonding pad is formed thereover. The input/output circuit is formed of MISFET elements in the nMISFET forming region and the pMISFET forming region, resistance elements in the resistance element forming regions and diode elements in the diode element forming regions functioning as protective elements. A wiring connected to the protective elements and positioned under the grounding wiring and the power supply wiring is pulled out in a pulling-out region between the nMISFET forming region and the pMISFET forming region and between the grounding wiring and the power supply wiring to be connected to the conductive layer.Type: GrantFiled: August 27, 2013Date of Patent: February 3, 2015Assignee: Renesas Electronics CorporationInventors: Takahiro Hayashi, Shunsuke Toyoshima, Kazuo Sakamoto, Naozumi Morino, Kazuo Tanaka
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Publication number: 20140354331Abstract: A semiconductor integrated circuit device comprises I/O cells arranged around a core region. Each of the I/O cells comprises a level shifter circuit, an I/O logic circuit, and an I/O buffer circuit. An I/O logic region in which the I/O logic circuit is arranged and an I/O buffer region in which the I/O buffer circuit is arranged overlap with a region in which a pad for the I/O cell is arranged. The I/O logic region and the I/O buffer region are arranged side by side in a direction parallel to a side of the core region.Type: ApplicationFiled: August 15, 2014Publication date: December 4, 2014Inventors: Kazuo SAKAMOTO, Naozumi MORINO, Kazuo TANAKA, Hiroyasu ISHIZUKA
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Patent number: 8896129Abstract: A semiconductor device includes a substrate including a circuit region where a circuit element is formed, a multilayer wiring layer that is formed on the substrate and composed of a plurality of wiring layers and a plurality of via layers that are laminated, and an electrode pad that is formed on the multilayer wiring layer. An interlayer insulating film is formed in a region of a first wiring layer that is a top layer of the plurality of wiring layers, in the region the electrode pad and the first circuit region overlapping each other in a planar view of the electrode pad.Type: GrantFiled: February 15, 2013Date of Patent: November 25, 2014Assignee: Renesas Electronics CorporationInventors: Ryo Mori, Kazuki Fukuoka, Naozumi Morino, Yoshinori Deguchi
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Patent number: 8810278Abstract: A semiconductor integrated circuit device comprises I/O cells arranged around a core region. Each of the I/O cells comprises a level shifter circuit, an I/O logic circuit, and an I/O buffer circuit. An I/O logic region in which the I/O logic circuit is arranged and an I/O buffer region in which the I/O buffer circuit is arranged overlap with a region in which a pad for the I/O cell is arranged. The I/O logic region and the I/O buffer region are arranged side by side in a direction parallel to a side of the core region.Type: GrantFiled: October 18, 2012Date of Patent: August 19, 2014Assignee: Renesas Electronics CorporationInventors: Kazuo Sakamoto, Naozumi Morino, Kazuo Tanaka, Hiroyasu Ishizuka
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Publication number: 20140193954Abstract: The reliability of a semiconductor device is to be improved. A microcomputer chip (semiconductor chip) having a plurality of pads formed on a main surface thereof is mounted over an upper surface of a wiring substrate in an opposed state of the chip main surface to the substrate upper surface. Pads coupled to a plurality of terminals (bonding leads) formed over the substrate upper surface comprise a plurality of first pads in which a unique electric current different from the electric current flowing through other pads flows and a plurality of second pads in which an electric current common to the pads flows or does not flow. Another first pad of the first pads or one of the second pads are arranged next to the first pad. The first pads are electrically coupled to a plurality of bonding leads respectively via a plurality of bumps (first conductive members), while the second pads are bonded to the terminals via a plurality of bumps (second conductive members).Type: ApplicationFiled: March 11, 2014Publication date: July 10, 2014Applicant: Renesas Electronics CorporationInventors: Naoto Taoka, Atsushi Nakamura, Naozumi Morino, Toshikazu Ishikawa, Nobuhiro Kinoshita