Abstract: There is provided a technology which allows improvements in manufacturing yield and product reliability in a semiconductor device having a triple well structure. A shallow p-type well is formed in a region different from respective regions in a p-type substrate where a deep n-type well, a shallow p-type well, and a shallow n-type well are formed. A p-type diffusion tap formed in the shallow p-type well is wired to a p-type diffusion tap formed in a shallow n-type well in the deep n-type well using an interconnection in a second layer. The respective gate electrodes of an nMIS and a pMIS each formed in the deep n-type well are coupled to the respective drain electrodes of an nMIS and a pMIS each formed in the substrate using an interconnection in a second or higher order layer.

Abstract: A technique which can improve manufacturing yield and product reliability is provided in a semiconductor device having a triple well structure. An inverter circuit which includes an n-channel type field effect transistor formed in a shallow p-type well and a p-channel type field effect transistor formed in a shallow n-type well, and does not contribute to circuit operations is provided in a deep n-type well formed in a p-type substrate; the shallow p-type well is connected to the substrate using a wiring of a first layer; and the gate electrode of the p-channel type field effect transistor and the gate electrode of the n-channel type field effect transistor are connected to the shallow n-type well using a wiring of an uppermost layer.

Abstract: A microcomputer is provided having a memory card interface capable of correctly latching data even when a card such as an MMC card is connected thereto. In the microcomputer having an interface with an external device such as a memory card, the interface unit is provided with an output driver connected to an external terminal for outputting a clock signal to output the clock signal and with an equivalent load circuit capable of imparting, to the clock signal extracted from an arbitrary position in a stage previous to the output driver in a clock signal path, delay equivalent to delay resulting from an external load connected to the external terminal in order to generate a clock signal for latching data inputted from the memory card.

Abstract: The present invention has for its purpose to provide a technique capable of reducing planar dimension of the semiconductor device. An input/output circuit is formed over the semiconductor substrate, a grounding wiring and a power supply wiring pass over the input/output circuit, and a conductive layer for a bonding pad is formed thereover. The input/output circuit is formed of MISFET elements in the nMISFET forming region and the pMISFET forming region, resistance elements in the resistance element forming regions and diode elements in the diode element forming regions functioning as protective elements. A wiring connected to the protective elements and positioned under the grounding wiring and the power supply wiring is pulled out in a pulling-out region between the nMISFET forming region and the pMISFET forming region and between the grounding wiring and the power supply wiring to be connected to the conductive layer.

Abstract: A microcomputer is provided having a memory card interface capable of correctly latching data even when a card such as an MMC card is connected thereto. In the microcomputer having an interface with an external device such as a memory card, the interface unit is provided with an output driver connected to an external terminal for outputting a clock signal to output the clock signal and with an equivalent load circuit capable of imparting, to the clock signal extracted from an arbitrary position in a stage previous to the output driver in a clock signal path, delay equivalent to delay resulting from an external load connected to the external terminal in order to generate a clock signal for latching data inputted from the memory card.

Abstract: The present invention is directed to assure an initial state of a circuit until a power supply voltage is stabilized at the time of power-on and to prevent an output circuit of an external input/output buffer circuit from performing erroneous operation at the time of setting a predetermined register value or the like to an initial value. A power supply detecting circuit outputs a power supply voltage detection signal indicating that a power supply voltage supplied from the outside enters a predetermined state. A power on reset circuit receives the power supply voltage detection signal, instructs an initial setting operation of the internal circuit at a predetermined timing and, in response to completion of the initial setting operation of the internal circuit, changes an external input/output buffer circuit from a high impedance state to an operable state. Consequently, when the external input/output buffer circuit becomes operable, the initial setting of the internal circuit has already completed.

Abstract: The present invention is directed to assure an initial state of a circuit until a power supply voltage is stabilized at the time of power-on and to prevent an output circuit of an external input/output buffer circuit from performing erroneous operation at the time of setting a predetermined register value or the like to an initial value. A power supply detecting circuit outputs a power supply voltage detection signal indicating that a power supply voltage supplied from the outside enters a predetermined state. A power on reset circuit receives the power supply voltage detection signal, instructs an initial setting operation of the internal circuit at a predetermined timing and, in response to completion of the initial setting operation of the internal circuit, changes an external input/output buffer circuit from a high impedance state to an operable state. Consequently, when the external input/output buffer circuit becomes operable, the initial setting of the internal circuit has already completed.

Abstract: A semiconductor device uses a package substrate on which bonding leads are formed respectively corresponding to bonding pads for address and data which are distributed to opposing first and second sides of a memory chip and address terminals and data terminals which are connected to the bonding leads. The semiconductor device further includes an address output circuit and a data input/output circuit which also serves for memory access and a signal processing circuit having a data processing function. A semiconductor chip having bonding pads connected to the bonding leads corresponding to the address terminals of the package substrate and bonding pads connected to the bonding leads corresponding to the data terminals of the package substrate and distributed to two sides out of four sides and the above-mentioned memory chip are mounted on the package substrate in a stacked structure.

Abstract: A technique which reduces the influence of external noise such as crosstalk noise in a semiconductor device to prevent a circuit from malfunctioning. A true signal wire and a bar signal wire which are susceptible to noise and part of an input signal line to a level shifter circuit, and shield wires for shielding these signal wires are laid on an I/O cell. Such I/O cells are placed side by side to complete a true signal wire connection and a bar signal wire connection. These wires are arranged in a way to pass over a plurality of I/O cells and are parallel to each other or multilayered.

Abstract: The present invention has for its purpose to provide a technique capable of reducing planar dimension of the semiconductor device. An input/output circuit is formed over the semiconductor substrate, a grounding wiring and a power supply wiring pass over the input/output circuit, and a conductive layer for a bonding pad is formed thereover. The input/output circuit is formed of MISFET elements in the nMISFET forming region and the pMISFET forming region, resistance elements in the resistance element forming regions and diode elements in the diode element forming regions functioning as protective elements. A wiring connected to the protective elements and positioned under the grounding wiring and the power supply wiring is pulled out in a pulling-out region between the nMISFET forming region and the pMISFET forming region and between the grounding wiring and the power supply wiring to be connected to the conductive layer.

Abstract: The present invention is directed to assure an initial state of a circuit until a power supply voltage is stabilized at the time of power-on and to prevent an output circuit of an external input/output buffer circuit from performing erroneous operation at the time of setting a predetermined register value or the like to an initial value. A power supply detecting circuit outputs a power supply voltage detection signal indicating that a power supply voltage supplied from the outside enters a predetermined state. A power on reset circuit receives the power supply voltage detection signal, instructs an initial setting operation of the internal circuit at a predetermined timing and, in response to completion of the initial setting operation of the internal circuit, changes an external input/output buffer circuit from a high impedance state to an operable state. Consequently, when the external input/output buffer circuit becomes operable, the initial setting of the internal circuit has already completed.

Abstract: The present invention provides a semiconductor device having a stacked structure which realizes the miniaturization of a contour size and the reduction of thickness. The present invention also provides a semiconductor device which realizes high performance and high reliability in addition to the miniaturization of the contour size. The semiconductor device uses a package substrate on which bonding leads which are formed respectively corresponding to bonding pads for address and data which are distributed to opposing first and second sides of a memory chip and address terminals and data terminals which are connected to the bonding leads are formed. The semiconductor device further includes an address output circuit and a data input/output circuit which are also served for memory access and a signal processing circuit having a data processing function.

Abstract: A semiconductor device uses a package substrate on which bonding leads are formed respectively corresponding to bonding pads for address and data which are distributed to opposing first and second sides of a memory chip and address terminals and data terminals which are connected to the bonding leads. The semiconductor device further includes an address output circuit and a data input/output circuit which also serves for memory access and a signal processing circuit having a data processing function. A semiconductor chip having bonding pads connected to the bonding leads corresponding to the address terminals of the package substrate and bonding pads connected to the bonding leads corresponding to the data terminals of the package substrate and distributed to two sides out of four sides and the above-mentioned memory chip are mounted on the package substrate in a stacked structure.

Abstract: A microcomputer is provided having a memory card interface capable of correctly latching data even when a card such as an MMC card is connected thereto. In the microcomputer having an interface with an external device such as a memory card, the interface unit is provided with an output driver connected to an external terminal for outputting a clock signal to output the clock signal and with an equivalent load circuit capable of imparting, to the clock signal extracted from an arbitrary position in a stage previous to the output driver in a clock signal path, delay equivalent to delay resulting from an external load connected to the external terminal in order to generate a clock signal for latching data inputted from the memory card.

Abstract: The present invention provides a semiconductor device having a stacked structure which realizes the miniaturization of a contour size and the reduction of thickness. The present invention also provides a semiconductor device which realizes high performance and high reliability in addition to the miniaturization of the contour size. The semiconductor device uses a package substrate on which bonding leads which are formed respectively corresponding to bonding pads for address and data which are distributed to opposing first and second sides of a memory chip and address terminals and data terminals which are connected to the bonding leads are formed. The semiconductor device further includes an address output circuit and a data input/output circuit which are also served for memory access and a signal processing circuit having a data processing function.