Abstract: A method for manufacturing a high performance bipolar device and the resulting structure which has a very small emitter-base spacing is described. The small emitter-base spacing, reduces the base resistance compared to earlier device spacing and thereby improves the performance of the bipolar device. The method involves providing a silicon semiconductor body having regions of monocrystalline silicon isolated from one another by isolation regions and a buried subcollector therein. A base region is formed in the isolated monocrystalline silicon. A mask is formed on the surface of the silicon body covering those regions designated to be the emitter and collector reach-through regions. A doped polycrystalline silicon layer is then formed through the mask covering the base region and making ohmic contact thereto. An insulating layer is formed over the polysilicon layer. The mask is removed from those regions designated to be the emitter and collector reach-through regions.

Abstract: A method is given for fabricating vertical NPN and PNP structures on the same semiconductor body. The method involves providing a monocrystalline semiconductor substrate having regions of monocrystalline silicon isolated from one another by isolation regions. Buried regions are formed overlapping the juncture of the substrate and epitaxial layer and are located in at least one of the regions of isolated monocrystalline silicon. The P base region in the NPN designated regions and a P reach-through in the PNP designated regions are formed simultaneously. The emitter region in the NPN regions and base contact region in the PNP regions are then formed simultaneously. The P emitter region in the PNP regions is then implanted by suitable ion implantation techniques. A Schottky Barrier collector contact in the PNP regions are formed. Electrical contacts are then made to the PNP and NPN transistor elements. A PNP device may be fabricated without the formation of an NPN device if it is so desired.

Abstract: A two phase charge coupled device memory array wherein the storage capacity is increased by using multiple levels of charge storage within a given cell. A voltage waveform generator capable of producing one of four different voltages is utilized to input and output charge in the multiple level charge method. In determining the level of charge stored within a given cell in the array, the voltage difference between a reference cell and an adjacent addressing cell is used. By determining the voltage level of the addressing cell at which charge overflows the reference cell and counting the number of times it overflows as the voltage generator is successively stepped through its four voltage levels, the level of the original charge input to a given cell can be determined. To make the multiple level scheme independent of process parameters and temperature, the same two cells are utilized for both input and output functions. Various other cells are provided to block and route charge with respect to the array.

Abstract: A Schottky barrier diode having an encircling floating polycrystalline silicon gate which becomes charged upon avalanche breakdown of the diode. The gate is self-aligned with respect to the Schottky barrier diode metal so that the gate uniformly overhangs the depletion area in the semiconductor when the diode is reverse biased. The gate is insulated from the semiconductor material and from the metal by dielectric layers including silicon dioxide and silicon nitride.