Patents by Inventor Narayan Srinivasa

Narayan Srinivasa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9111182
    Abstract: Described is a system for multispectral image processing with spiking dynamics. For example, the system receives an input image and compresses the image through space and spectrally variant sampling. Center-surround dynamics are modeled to control high dynamic ranges of the image and provide gain control. Further, habituative dynamics are modeled to produce outputs specialized for static or dynamic image content. Finally, neural spikes are generated based on the habituative dynamics. The neural spikes are saved or provided to other systems for further image processing.
    Type: Grant
    Filed: September 6, 2013
    Date of Patent: August 18, 2015
    Assignee: HRL Laboratories, LLC
    Inventors: Suhas E. Chelian, Narayan Srinivasa
  • Patent number: 8996431
    Abstract: A spike domain asynchronous neuron circuit includes a first spike to exponential circuit for emulating kinetic dynamics at a neuron input and converting voltage spikes into exponentials, a first adjustable gain circuit for emulating homeostatic plasticity coupled to the first voltage-type spike exponential output and having a first current output, a neuron core circuit coupled to the first current output for emulating a neuron core and having a spike encoded voltage output, a filter and comparator circuit coupled to the spike encoded voltage output and having a gain control output coupled to the first adjustable gain circuit for controlling a gain of the first adjustable gain circuit, and an adjustable delay circuit for emulating an axonal delay coupled to the spike encoded voltage output and having an axonal delay output.
    Type: Grant
    Filed: November 16, 2012
    Date of Patent: March 31, 2015
    Assignee: HRL Laboratories, LLC
    Inventors: Jose Cruz-Albrecht, Michael W. Yung, Narayan Srinivasa
  • Patent number: 8977578
    Abstract: A synaptic time-multiplexed (STM) neuromorphic network includes a neural fabric that includes nodes and switches to define inter-nodal connections between selected nodes of the neural fabric. The STM neuromorphic network further includes a neuromorphic controller to form subsets of a set of the inter-nodal connections representing a fully connected neural network. Each subset is formed during a different time slot of a plurality of time slots of a time multiplexing cycle of the STM neuromorphic network. In combination, the inter-nodal connection subsets implement the fully connected neural network. A method of synaptic time multiplexing a neuromorphic network includes providing the neural fabric and forming the subsets of the set of inter-nodal connections.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: March 10, 2015
    Assignee: HRL Laboratories, LLC
    Inventors: Jose M. Cruz-Albrecht, Narayan Srinivasa, Peter Petre, Youngkwan Cho, Aleksey Nogin
  • Patent number: 8959040
    Abstract: A spike timing dependent plasticity (STDP) apparatus, neuromorphic synapse system and a method provide STDP processing of spike signals. The STDP apparatus includes a first leaky integrator to receive a first spike signal and a second leaky integrator to receive a second spike signal. An output of the first leaky integrator is gated according to the second spike signal to produce a first gated integrated signal and an output of the second leaky integrator is gated according to the first spike signal to produce a second gated integrated signal. The STDP apparatus further includes an output integrator to integrate a difference of the first and second gated integrated signals to produce a weighted signal. The system includes a synapse core and the STDP apparatus. The method includes integrating the spike signals, gating the integrated signals and integrating a difference of the gated integrated signals.
    Type: Grant
    Filed: March 8, 2012
    Date of Patent: February 17, 2015
    Assignee: HRL Laboratories, LLC
    Inventors: Jose Cruz-Albrecht, Peter Petre, Narayan Srinivasa
  • Publication number: 20150026110
    Abstract: A neural network, wherein a portion of the neural network comprises: a first array having a first number of neurons, wherein the dendrite of each neuron of the first array is provided for receiving an input signal indicating that a measured parameter gets closer to a predetermined value assigned to said neuron; and a second array having a second number of neurons, wherein the second number is smaller than the first number, the dendrite of each neuron of the second array forming an excitatory STDP synapse with the axon of a plurality of neurons of the first array; the dendrite of each neuron of the second array forming an excitatory STDP synapse with the axon of neighboring neurons of the second array.
    Type: Application
    Filed: August 30, 2013
    Publication date: January 22, 2015
    Applicant: HRL LABORATORIES, LLC
    Inventors: Narayan Srinivasa, Youngkwan Cho
  • Patent number: 8930291
    Abstract: A cortical neuromorphic network, system and method employ a plurality of neuromorphic nodes arranged in a network layer. The cortical neuromorphic network includes a neuromorphic node of the network layer in which the neuromorphic node includes a spike timing dependent plasticity (STDP) synapse and a neuromorphic neuron. The neuromorphic node is configured to receive a feedforward spike signal from selected ones of a plurality of input neurons of an input layer and to provide an output spike signal as a recurrent spike signal to the neuromorphic nodes of the network layer. A combination of the recurrent and feedforward spike signals is an excitatory spike signal of the neuromorphic node. The cortical neuromorphic system includes the neuromorphic nodes configured to operate according to a cycle and time slots of synaptic time multiplexing. The method includes receiving and weighting the excitatory spike signal using the STDP synapse and producing the output spike signal.
    Type: Grant
    Filed: December 7, 2012
    Date of Patent: January 6, 2015
    Assignee: HRL Laboratories, LLC
    Inventors: Narayan Srinivasa, Jose Cruz-Albrecht, Youngkwon Cho
  • Publication number: 20140344202
    Abstract: A neural model for reinforcement-learning and for action-selection includes a plurality of channels, a population of input neurons in each of the channels, a population of output neurons in each of the channels, each population of input neurons in each of the channels coupled to each population of output neurons in each of the channels, and a population of reward neurons in each of the channels. Each channel of a population of reward neurons receives input from an environmental input, and is coupled only to output neurons in a channel that the reward neuron is part of. If the environmental input for a channel is positive, the corresponding channel of a population of output neurons are rewarded and have their responses reinforced, otherwise the corresponding channel of a population of output neurons are punished and have their responses attenuated.
    Type: Application
    Filed: June 2, 2014
    Publication date: November 20, 2014
    Inventors: Corey M. THIBEAULT, Narayan Srinivasa
  • Publication number: 20140241211
    Abstract: A Multiple Input Multiple Output (MIMO) Orthogonal Frequency Division Multiplexing (OFDM) system for inter-device communication is described. Information data from each neuromorphic chip is coded and modulated, on the basis of destination, into different channels. The parallel signals in different channels are sent serially using TDM to a central router. After signal grouping by a central switching controller, each group of signals may be delivered to corresponding transmitter in the central router for transmission to a corresponding receiver in the neuromorphic chip using TDM.
    Type: Application
    Filed: February 27, 2013
    Publication date: August 28, 2014
    Applicant: HRL LABORATORIES, LLC.
    Inventors: Deying Zhang, Narayan Srinivasa
  • Patent number: 8774504
    Abstract: The present invention describes a system for recognizing objects from color images by detecting features of interest, classifying them according to previous objects' features that the system has been trained on, and finally drawing a boundary around them to separate each object from others in the image. Furthermore, local feature detection algorithms are applied to color images, outliers are removed, and resulting feature descriptors are clustered to achieve effective object recognition. Additionally, the present invention describes a system for extracting foreground objects and the correct rejection of the background from an image of a scene. Importantly, the present invention allows for changes to the camera viewpoint or lighting between training and test time. The system uses a supervised-learning algorithm and produces blobs of foreground objects that a recognition algorithm can then use for object detection/recognition.
    Type: Grant
    Filed: October 26, 2011
    Date of Patent: July 8, 2014
    Assignee: HRL Laboratories, LLC
    Inventors: Rashmi N. Sundareswara, Narayan Srinivasa
  • Patent number: 8762305
    Abstract: The present invention relates to a system for mapping external inputs and internal goals toward actions that solve problems or elicit external rewards. The present invention allows an instructor to test and train an agent to perform dynamic task selection (executive control) by using a schema that computes the agent's emotional and motivational states from reward/punishment inputs and sensory inputs (visual, auditory, kinematic, tactile, olfactory, somatosensory, and motor inputs). Specifically, the invention transforms the sensory inputs into unimodal and bimodal spatio-temporal schemas that are combined with the reward/punishment inputs and with the emotional and motivation states to create an external/internal schema (EXIN schema), that provides a compressed representation assessing the agent's emotions, motivations, and rewards. The invention uses the EXIN schema to create a motor schema to be executed by the agent to dynamically perform the task selected by the instructor.
    Type: Grant
    Filed: November 2, 2011
    Date of Patent: June 24, 2014
    Assignee: HRL Laboratories, LLC
    Inventors: Suhas E. Chelian, Narayan Srinivasa
  • Publication number: 20140156578
    Abstract: A neural network portion comprising N pre-synaptic neurons capable each of firing an action potential, wherein the number N can be encoded in a word of n bits; the neural network portion being provided for, upon firing of a number F of pre-synaptic neurons in a predetermined period of time: if F.n<N, generating a first type message, the message comprising a unique address for each pre-synaptic neuron having fired in said predetermined period of time, each address being encoded as a word of n bits; and if F.n>N, generating a second type message, the message comprising N bits and being encoded in words of n bits, wherein each one of said N pre-synaptic neurons is represented by a unique bit, each bit having a first value if the pre-synaptic neuron represented by the bit fired in said predetermined period of time, and a second value otherwise.
    Type: Application
    Filed: December 2, 2013
    Publication date: June 5, 2014
    Applicant: HRL LABORATORIES, LLC
    Inventors: Corey Thibeault, Kirill Minkovich, Narayan Srinivasa
  • Publication number: 20140032460
    Abstract: A spike domain asynchronous neuron circuit includes a first spike to exponential circuit for emulating kinetic dynamics at a neuron input and converting voltage spikes into exponentials, a first adjustable gain circuit for emulating homeostatic plasticity coupled to the first voltage-type spike exponential output and having a first current output, a neuron core circuit coupled to the first current output for emulating a neuron core and having a spike encoded voltage output, a filter and comparator circuit coupled to the spike encoded voltage output and having a gain control output coupled to the first adjustable gain circuit for controlling a gain of the first adjustable gain circuit, and an adjustable delay circuit for emulating an axonal delay coupled to the spike encoded voltage output and having an axonal delay output.
    Type: Application
    Filed: November 16, 2012
    Publication date: January 30, 2014
    Applicant: HRL LABRORATORIES, LLC
    Inventors: Jose Cruz-Albrecht, Michael W. Yung, Narayan Srinivasa
  • Patent number: 8595157
    Abstract: A spike domain circuit responsive to analog and/or spike domain input signals. The spike domain circuit has a hysteresis quantizer for generating a spike domain output signal z(t); a one bit DAC having an input which is coupled to receive the spike domain output signal z(t) output by the hysteresis quantizer and having an output which is coupled to a current summing node; and a second order filter stage having two inputs, one of said two inputs being coupled to receive the spike domain output signal z(t) output by the hysteresis quantizer and the other of the two inputs being coupled to receive current summed at said current summing node. The second order filter stage has an output coupled to an input of the hysteresis quantizer. The current summing node also receives signals related to the analog and/or spike domain input signals to which the circuit is responsive. The circuit may serve as a neural node and many such circuits may be utilized together to model neurons with complex biological dynamics.
    Type: Grant
    Filed: June 2, 2011
    Date of Patent: November 26, 2013
    Assignee: HRL Laboratories, LLC
    Inventors: Jose Cruz-Albrecht, Peter Petre, Narayan Srinivasa
  • Patent number: 8577815
    Abstract: A method and system for characterizing, detecting, and predicting or forecasting multiple target events from a past history of these events includes compressing temporal data streams into self-organizing map (SOM) clusters, and determining trajectories of the temporal streams via the clusters to predict the multiple target events. The system includes an evolutionary multi-objective optimization (EMO) module for processing the temporal data streams, which are obtained from a plurality of heterogeneous domains; a SOM module for characterizing the temporal data streams into self-organizing map clusters; and a target event prediction (TEP) module for generating prediction models of the map clusters. The SOM module employs a vector quantization method that places a set of vectors on a low-dimensional grid in an ordered fashion. The prediction models each include trajectories of the temporal data streams, and the system predicts the multiple target events using the trajectories.
    Type: Grant
    Filed: October 23, 2009
    Date of Patent: November 5, 2013
    Assignee: GM Global Technology Operations LLC
    Inventors: Leandro G. Barajas, Youngkwan Cho, Narayan Srinivasa
  • Patent number: 8468104
    Abstract: Described is a system for anomaly detection to detect an anomalous object in an image, such as a concealed object beneath a person's clothing. The system is configured to receive, in a processor, at least one streaming peaked curve (R) representative of a difference between an input and a chosen category for a given feature. A degree of match is then generated between the input and the chosen category for all features. Finally, the degree of match is compared against a predetermined anomaly threshold and, if the degree of match exceeds the predetermined anomaly threshold, then the current feature is designated as an anomaly.
    Type: Grant
    Filed: December 2, 2009
    Date of Patent: June 18, 2013
    Assignee: HRL Laboratories, LLC
    Inventors: Suhas E. Chelian, Narayan Srinivasa
  • Patent number: 8406989
    Abstract: A method for adaptive obstacle avoidance for articulated redundant robots is disclosed. The method comprises acts of calculating an obstacle avoidance vector for each of a set of limbs in a robot arm, and then applying the obstacle avoidance vector to constrain the inverse model in a robot controller. The obstacle avoidance vector incorporates factors including: (1) a distance and direction of each of a set of obstacles to the limb; and (2) when the limb is part of a kinematic chain of limbs, contributions from the obstacle avoidance vectors of all peripheral limbs in the kinematic chain. The method of the present invention was designed for use with the DIRECT model robot controller, but the method is generally applicable to any of a variety of robot controllers known in the art.
    Type: Grant
    Filed: February 13, 2009
    Date of Patent: March 26, 2013
    Assignee: HRL Laboratories, LLC
    Inventors: Rajan Bhattacharyya, Narayan Srinivasa
  • Patent number: 8390500
    Abstract: An asynchronous pulse processing (APP) apparatus, APP system and a method of signal reverberation employ asynchronous pulse processing to provide signal reverberation. The APP apparatus includes a gain block configured to scale an input signal by a first scale value and a summation block configured to produce a composite signal. The composite signal represents the scaled input signal minus an input summation signal multiplied by a reverberation signal, minus the reverberation signal scaled by a second scale value, and plus a function-modified feedback signal. The APP apparatus further includes an integrator and a time encoder configured to produce the reverberation signal from the composite signal. The APP system includes a plurality of APP apparatuses as APP channels. The method of signal reverberation includes generating a composite signal from a scaled input signal, and integrating and time encoding the composite signal to produce a reverberation signal.
    Type: Grant
    Filed: June 14, 2010
    Date of Patent: March 5, 2013
    Assignee: HRL Laboratories, LLC
    Inventors: Narayan Srinivasa, Jose Cruz-Albrecht, Peter Petre
  • Publication number: 20120310871
    Abstract: A spike domain circuit responsive to analog and/or spike domain input signals. The spike domain circuit has a hysteresis quantizer for generating a spike domain output signal z(t); a one bit DAC having an input which is coupled to receive the spike domain output signal z(t) output by the hysteresis quantizer and having an output which is coupled to a current summing node; and a second order filter stage having two inputs, one of said two inputs being coupled to receive the spike domain output signal z(t) output by the hysteresis quantizer and the other of the two inputs being coupled to receive current summed at said current summing node. The second order filter stage has an output coupled to an input of the hysteresis quantizer. The current summing node also receives signals related to the analog and/or spike domain input signals to which the circuit is responsive. The circuit may serve as a neural node and many such circuits may be utilized together to model neurons with complex biological dynamics.
    Type: Application
    Filed: June 2, 2011
    Publication date: December 6, 2012
    Applicant: HRL LABORATORIES, LLC
    Inventors: Jose Cruz-Albrecht, Peter Petre, Narayan Srinivasa
  • Patent number: 8204623
    Abstract: A planning approach for obstacle avoidance for a robot arm is disclosed. In particular, the invention relates to a planning approach for obstacle avoidance in complex environments for an articulated redundant robot arm which uses a set of via points surrounding an obstacle as an intermediary point between initial and target arm positions. Via points are generated using visual perception, and possible trajectories through the via points and to the target are rehearsed prior to execution of movement. The disclosed planning method solves the “local minima” problem in obstacle avoidance; a situation in which the obstacle avoidance vectors prevent the arm from making progress toward the target.
    Type: Grant
    Filed: October 13, 2009
    Date of Patent: June 19, 2012
    Assignee: HRL Laboratories, LLC
    Inventors: Rajan Bhattacharyya, Narayan Srinivasa
  • Patent number: 8174425
    Abstract: An asynchronous pulse processing (APP) apparatus, an APP system and a method of signal normalization employing APP provide signal normalization. The APP apparatus includes a gain block configured to scale an input signal by a first scale value and a summation block configured to produce a composite signal by subtracting from the scaled input signal each of a normalized signal scaled by a second scale value and the normalized signal multiplied by a summation signal. The APP apparatus further includes an integrator and a time encoder configured to produce the normalized signal from the composite signal. The APP system includes a plurality of APP apparatuses as APP channels. The method of signal normalization includes generating the composite signal from the scaled input signal and integrating and time encoding the composite signal to produce the normalized signal.
    Type: Grant
    Filed: June 14, 2010
    Date of Patent: May 8, 2012
    Assignee: HRL Laboratories, LLC
    Inventors: Narayan Srinivasa, Jose Cruz-Albrecht, Peter Petre