Patents by Inventor Narayan Srinivasa

Narayan Srinivasa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180005108
    Abstract: A circuit for emulating the behavior of biological neural circuits, the circuit including a plurality of nodes wherein each node comprises a neuron circuit, a time multiplexed synapse circuit coupled to an input of the neuron circuit, a time multiplexed short term plasticity (STP) circuit coupled to an input of the node and to the synapse circuit, a time multiplexed Spike Timing Dependent Plasticity (STDP) circuit coupled to the input of the node and to the synapse circuit, an output of the node coupled to the neuron circuit; and an interconnect fabric coupled between the plurality of nodes for providing coupling from the output of any node of the plurality of nodes to any input of any other node of the plurality of nodes.
    Type: Application
    Filed: June 30, 2016
    Publication date: January 4, 2018
    Applicant: HRL LABORATORIES, LLC
    Inventors: JOSE CRUZ-ALBRECHT, TIMOTHY DEROSIER, NARAYAN SRINIVASA
  • Publication number: 20170316310
    Abstract: Described is a system for decoding spiking reservoirs even when the spiking reservoir has continuous synaptic plasticity. The system uses a set of training patterns to train a neural network having a spiking reservoir comprised of spiking neurons. A test pattern duration d is estimated for a set of test patterns P, and each test pattern is presented to the spiking reservoir for a duration of d/P seconds. Output spikes from the spiking reservoir are generated via readout neurons. The output spikes are measured and the measurements are used to compute firing rate codes, each firing rate code corresponding to a test pattern in the set of test patterns P. The firing rate codes are used to decode performance of the neural network by computing a discriminability index (DI) to discriminate between test patterns in the set of test patterns P.
    Type: Application
    Filed: March 18, 2016
    Publication date: November 2, 2017
    Inventors: Youngkwan Cho, Narayan Srinivasa
  • Publication number: 20170316311
    Abstract: Described is a sparse inference module that can be incorporated into a deep learning system. For example, the deep learning system includes a plurality of hierarchical feature channel layers, each feature channel layer having a set of filters. A plurality of sparse inference modules can be included such that a sparse inference module resides electronically within each feature channel layer. Each sparse inference module is configured to receive data and match the data against a plurality of pattern templates to generate a degree of match value for each of the pattern templates, with the degree of match values being sparsified such that only those degree of match values that exceed a predetermined threshold, or a fixed number of the top degree of match values, are provided to subsequent feature channels in the plurality of hierarchical feature channels, while other, losing degree of match values are quenched to zero.
    Type: Application
    Filed: March 24, 2016
    Publication date: November 2, 2017
    Inventors: Praveen K. Pilly, Nigel D. Stepp, Narayan Srinivasa
  • Publication number: 20170316555
    Abstract: Described is a system for ghost removal in video footage. During operation, the system generates a background subtraction map and an original bounding box that surrounds a detected foreground object through background subtraction. A detected foreground map is then generated. The detected foreground map includes at least two detected foreground (DF) bounding boxes of detected foregrounds obtained by a difference of two consecutive frames in video footage. Further, the original bounding box is then trimmed into a trimmed box, the trimmed box being a smallest box that contains the at least two DF bounding boxes. The trimmed box is designated as containing a real-world object, which can then be used for object tracking.
    Type: Application
    Filed: April 6, 2017
    Publication date: November 2, 2017
    Inventors: Yongqiang Cao, Narayan Srinivasa
  • Patent number: 9721332
    Abstract: A convolution circuit includes: a plurality of input oscillators, each configured to: receive a corresponding analog input signal of a plurality of analog input signals; and output a corresponding spiking signal of a plurality of spiking signals, the corresponding spiking signal having a spiking rate in accordance with a magnitude of the corresponding analog input signal; a plurality of 1-bit DACs, each of the 1-bit DACs being configured to: receive the corresponding spiking signal of the plurality of spiking signals from a corresponding one of the input oscillators; and receive a corresponding weight of a convolution kernel comprising a plurality of weights; output a corresponding weighted output of a plurality of weighted outputs in accordance with the corresponding spiking signal and the corresponding weight; and an output oscillator configured to generate an output spike signal in accordance with the plurality of weighted outputs from the plurality of 1-bit DACs.
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: August 1, 2017
    Assignee: HRL Laboratories, LLC
    Inventors: Jose Cruz-Albrecht, Michael W. Yung, Narayan Srinivasa
  • Patent number: 9697462
    Abstract: A synaptic time-multiplexed (STM) neuromorphic network includes a neural fabric that includes nodes and switches to define inter-nodal connections between selected nodes of the neural fabric. The STM neuromorphic network further includes a neuromorphic controller to form subsets of a set of the inter-nodal connections representing a fully connected neural network. Each subset is formed during a different time slot of a plurality of time slots of a time multiplexing cycle of the STM neuromorphic network. In combination, the inter-nodal connection subsets implement the fully connected neural network. A method of synaptic time multiplexing a neuromorphic network includes providing the neural fabric and forming the subsets of the set of inter-nodal connections.
    Type: Grant
    Filed: January 3, 2015
    Date of Patent: July 4, 2017
    Assignee: HRL Laboratories, LLC
    Inventors: Jose M. Cruz-Albrecht, Narayan Srinivasa, Peter Petre, Youngkwan Cho, Aleksey Nogin
  • Patent number: 9566174
    Abstract: Described is a system for controlling a torque controlled prosthetic device given motor intent inferred from neuroimaging data. The system includes at least one torque controlled prosthetic device operably connected with one or more processors. Further, the system is configured to receive neuroimaging data of a user from a neuroimaging device and decode the neuroimaging data to infer spatial motion intent of the user, where the spatial motion intent includes desired motion commands of the torque controlled prosthetic device represented in a coordinate system. The system thereafter executes, with a prosthesis controller, the motion commands as torque commands to cause the torque controlled prosthetic device to move according to the spatial motion intent of the user.
    Type: Grant
    Filed: November 13, 2014
    Date of Patent: February 14, 2017
    Assignee: HRL Laboratories, LLC
    Inventors: Vincent De Sapio, Narayan Srinivasa
  • Publication number: 20160364643
    Abstract: A reconfigurable neural circuit includes a two dimensional array including a plurality of processing nodes, wherein each processing node includes a neuron circuit, a synapse circuit, a spike timing dependent plasticity (STDP) circuit, a weight memory for storing synaptic weights, the weight memory coupled to the synapse circuit, an interconnect fabric for interconnections to and from and between the neuron circuit, the synapse circuit, the STDP circuit, the weight memory, and between a respective node in the array and other processing nodes in the array, and a connectivity memory for storing interconnect routing controls coupled to the interconnect fabric.
    Type: Application
    Filed: August 6, 2014
    Publication date: December 15, 2016
    Applicant: HRL LABORATORIES LLC
    Inventors: Jose CRUZ-ALBRECHT, Timothy Derosier, Narayan Srinivasa
  • Patent number: 9515789
    Abstract: A Multiple Input Multiple Output (MIMO) Orthogonal Frequency Division Multiplexing (OFDM) system for inter-device communication is described. Information data from each neuromorphic chip is coded and modulated, on the basis of destination, into different channels. The parallel signals in different channels are sent serially using TDM to a central router. After signal grouping by a central switching controller, each group of signals may be delivered to corresponding transmitter in the central router for transmission to a corresponding receiver in the neuromorphic chip using TDM.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: December 6, 2016
    Assignee: HRL Laboratories, LLC
    Inventors: Deying Zhang, Narayan Srinivasa
  • Patent number: 9443189
    Abstract: Described is a system, method, and computer program product for feature detection with spiking dynamics. The system is configured to perform operations of first receiving an input pattern comprising a plurality of features. The input pattern is then translated into a spike-coded representation of the input pattern. The spike-coded representation of the input pattern is transferred to a feature detector layer of a feature detector network comprising a set of feature detector neurons having input weights. Each feature detector neuron in the set of feature detector neurons then competes for the feature detector neuron whose input weights best represent the input pattern. Finally, the input weights which compressively code frequently seen input patterns are updated according to a set of learning rules. Also presented is a novel set of rules that transform the functional properties of rate-coded models into the spiking domain.
    Type: Grant
    Filed: January 16, 2013
    Date of Patent: September 13, 2016
    Assignee: HRL Laboratories, LLC
    Inventors: Suhas E. Chelian, Narayan Srinivasa
  • Patent number: 9430737
    Abstract: A neural network, wherein a portion of the neural network comprises: a first array having a first number of neurons, wherein the dendrite of each neuron of the first array is provided for receiving an input signal indicating that a measured parameter gets closer to a predetermined value assigned to said neuron; and a second array having a second number of neurons, wherein the second number is smaller than the first number, the dendrite of each neuron of the second array forming an excitatory STDP synapse with the axon of a plurality of neurons of the first array; the dendrite of each neuron of the second array forming an excitatory STDP synapse with the axon of neighboring neurons of the second array.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: August 30, 2016
    Assignee: HRL Laboratories, LLC
    Inventors: Narayan Srinivasa, Youngkwan Cho
  • Patent number: 9430736
    Abstract: A neural network portion comprising N pre-synaptic neurons capable each of firing an action potential, wherein the number N can be encoded in a word of n bits; the neural network portion being provided for, upon firing of a number F of pre-synaptic neurons in a predetermined period of time: if F.n<N, generating a first type message, the message comprising a unique address for each pre-synaptic neuron having fired in said predetermined period of time, each address being encoded as a word of n bits; and if F.n>N, generating a second type message, the message comprising N bits and being encoded in words of n bits, wherein each one of said N pre-synaptic neurons is represented by a unique bit, each bit having a first value if the pre-synaptic neuron represented by the bit fired in said predetermined period of time, and a second value otherwise.
    Type: Grant
    Filed: December 2, 2013
    Date of Patent: August 30, 2016
    Assignee: HRL Laboratories, LLC
    Inventors: Corey Thibeault, Kirill Minkovich, Narayan Srinivasa
  • Publication number: 20160239947
    Abstract: A convolution circuit includes: a plurality of input oscillators, each configured to: receive a corresponding analog input signal of a plurality of analog input signals; and output a corresponding spiking signal of a plurality of spiking signals, the corresponding spiking signal having a spiking rate in accordance with a magnitude of the corresponding analog input signal; a plurality of 1-bit DACs, each of the 1-bit DACs being configured to: receive the corresponding spiking signal of the plurality of spiking signals from a corresponding one of the input oscillators; and receive a corresponding weight of a convolution kernel comprising a plurality of weights; output a corresponding weighted output of a plurality of weighted outputs in accordance with the corresponding spiking signal and the corresponding weight; and an output oscillator configured to generate an output spike signal in accordance with the plurality of weighted outputs from the plurality of 1-bit DACs.
    Type: Application
    Filed: February 12, 2016
    Publication date: August 18, 2016
    Inventors: Jose Cruz-Albrecht, Michael W. Yung, Narayan Srinivasa
  • Patent number: 9412051
    Abstract: Neuromorphic image processing employs neuromorphic neurons arranged as relay neurons, interneurons and reticular neurons to process image data. A neuromorphic image processing channel includes relay neurons and interneurons to receive spiking input signals. The interneurons provide feed-forward inhibition to the relay neurons. The neuromorphic image processing channel also includes reticular neurons to receive output spiking signals from and to provide feedback inhibition to the relay neurons. A neuromorphic image processing system includes a first neuromorphic image processing (NIP) channel to receive a first set of spiking input signals and a second NIP channel to receive a second set of spiking input signals. The neuromorphic image processing system also includes reticular neurons to receive output spiking signals from and to provide feedback inhibition to both the first and second NIP channels.
    Type: Grant
    Filed: June 4, 2014
    Date of Patent: August 9, 2016
    Assignee: HRL Laboratories, LLC
    Inventors: Suhas E. Chelian, Narayan Srinivasa
  • Patent number: 9349092
    Abstract: A neural model for reinforcement-learning and for action-selection includes a plurality of channels, a population of input neurons in each of the channels, a population of output neurons in each of the channels, each population of input neurons in each of the channels coupled to each population of output neurons in each of the channels, and a population of reward neurons in each of the channels. Each channel of a population of reward neurons receives input from an environmental input, and is coupled only to output neurons in a channel that the reward neuron is part of. If the environmental input for a channel is positive, the corresponding channel of a population of output neurons are rewarded and have their responses reinforced, otherwise the corresponding channel of a population of output neurons are punished and have their responses attenuated.
    Type: Grant
    Filed: June 2, 2014
    Date of Patent: May 24, 2016
    Assignee: HRL Laboratories, LLC
    Inventors: Corey M. Thibeault, Narayan Srinivasa
  • Patent number: 9275328
    Abstract: A neuromorphic compiler includes a placement module to provide analytic placement of neurons in a neural network description. The analytic placement is to produce placed neurons. The neuromorphic compiler further includes a smoothing module to perform diffusion-based smoothing of the placed neurons; a legalization module to adjust locations of the placed neurons to correspond to legal locations of neuromorphic neurons within a neural fabric; and a simulated annealing module to refine locations of the placed neurons within the neural fabric using simulated annealing following location adjustment by the legalization module. The neural fabric is to implement a synaptic time-multiplexed (STM) neuromorphic network.
    Type: Grant
    Filed: May 2, 2013
    Date of Patent: March 1, 2016
    Assignee: HRL Laboratories, LLC
    Inventors: Kirill Minkovich, Aleksey Nogin, Yougkwan Cho, Narayan Srinivasa
  • Patent number: 9262843
    Abstract: A circuit for detecting features in an image, the circuit including M time encoders, each time encoder having two inputs, Xi and Ti, where Xi is an ith element of an input vector X1 XM of the image and Ti is an ith element of a template vector T1 TM, and having an oscillatory output, wherein when the input vector X1 XM and the template vector T1 TM are more matched, the oscillatory outputs of the time encoders are more synchronized, and wherein when the input vector X1 XM and the template vector T1 TM are less matched, the oscillatory outputs of the time encoders are less synchronized.
    Type: Grant
    Filed: March 10, 2014
    Date of Patent: February 16, 2016
    Assignee: HRL Laboratories, LLC
    Inventors: Jose Cruz-Albrecht, Narayan Srinivasa
  • Patent number: 9224070
    Abstract: The present invention describes a system for recognizing objects from color images by detecting features of interest, classifying them according to previous objects' features that the system has been trained on, and finally drawing a boundary around them to separate each object from others in the image. Furthermore, local feature detection algorithms are applied to color images, outliers are removed, and resulting feature descriptors are clustered to achieve effective object recognition. Additionally, the present invention describes a system for extracting foreground objects and the correct rejection of the background from an image of a scene. Importantly, the present invention allows for changes to the camera viewpoint or lighting between training and test time. The system uses a supervised-learning algorithm and produces blobs of foreground objects that a recognition algorithm can then use for object detection/recognition.
    Type: Grant
    Filed: May 29, 2014
    Date of Patent: December 29, 2015
    Assignee: HRL Laboratories, LLC
    Inventors: Rashmi. N Sundareswara, Narayan Srinivasa
  • Publication number: 20150302296
    Abstract: A neural model for reinforcement-learning and for action-selection includes a plurality of channels, a population of input neurons in each of the channels, a population of output neurons in each of the channels, each population of input neurons in each of the channels coupled to each population of output neurons in each of the channels, and a population of reward neurons in each of the channels. Each channel of a population of reward neurons receives input from an environmental input, and is coupled only to output neurons in a channel that the reward neuron is part of. If the environmental input for a channel is positive, the corresponding channel of a population of output neurons are rewarded and have their responses reinforced, otherwise the corresponding channel of a population of output neurons are punished and have their responses attenuated.
    Type: Application
    Filed: May 16, 2013
    Publication date: October 22, 2015
    Applicant: HRL LABORATORIES, LLC
    Inventors: Corey M. Thibeault, Narayan Srinivasa
  • Patent number: 9111182
    Abstract: Described is a system for multispectral image processing with spiking dynamics. For example, the system receives an input image and compresses the image through space and spectrally variant sampling. Center-surround dynamics are modeled to control high dynamic ranges of the image and provide gain control. Further, habituative dynamics are modeled to produce outputs specialized for static or dynamic image content. Finally, neural spikes are generated based on the habituative dynamics. The neural spikes are saved or provided to other systems for further image processing.
    Type: Grant
    Filed: September 6, 2013
    Date of Patent: August 18, 2015
    Assignee: HRL Laboratories, LLC
    Inventors: Suhas E. Chelian, Narayan Srinivasa