Abstract: In an embodiment, a method for performing scan includes: entering scan mode; receiving a test pattern; applying the test pattern through a first scan chain by asserting and deasserting a scan enable signal to respectively perform shift and capture operations to the first scan chain; while applying the test pattern through the first scan chain, controlling a further scan flip-flop with the first scan chain without transitioning a further scan enable input of the further scan flip-flop; and evaluating an output of the first scan chain to detect faults.

Abstract: In an embodiment, a method for managing self-tests in an integrated circuit (IC) includes: receiving built-in-self-test (BIST) configuration data; configuring a first clock to a first frequency based on the BIST configuration data; performing a first BIST test at the first frequency; configuring a second clock to a second frequency that is different from the first frequency; and performing a second BIST test at the second frequency.

Abstract: In an embodiment, a method for performing scan includes: entering scan mode; receiving a test pattern; applying the test pattern through a first scan chain by asserting and deasserting a scan enable signal to respectively perform shift and capture operations to the first scan chain; while applying the test pattern through the first scan chain, controlling a further scan flip-flop with the first scan chain without transitioning a further scan enable input of the further scan flip-flop; and evaluating an output of the first scan chain to detect faults.

Abstract: In an embodiment, a method for performing scan testing includes: generating first and second scan clock signals; providing the first and second scan clock signals to first and second scan chains, respectively, where the first and second scan clock signals includes respective first shift pulses when a scan enable signal is asserted, and respective first capture pulses when the scan enable signal is deasserted, where the first shift pulse of the first and second scan clock signals correspond to a first clock pulse of a first clock signal, where the first capture pulse of the first scan clock signal corresponds to a second clock pulse of the first clock signal, and where the first capture pulse of the second scan clock signal corresponds to a first clock pulse of a second clock signal different from the first clock signal.

Abstract: Described herein are integrated circuit chips having test circuitry designed such that independently selectable testing of different power domains using a same scan chain compressor-decompressor circuit may be performed. Also disclosed herein are integrated circuit chips having test circuitry designed such that independently selectable testing of different power domains using multiple different scan chain compressor-decompressor circuits may be performed.

Abstract: Systems and methods for contextual alerts during ground operations are provided. The system generates unique alerts for each type of hot-spot and commands a display system to render an image of the route, the relevant signage features, and the hot-spots. The system receives an assigned runway and references an airport features database to construct a route and travel direction for the aircraft. The system analyzes the signage features associated with the route and identifies the relevant signage features. The system processes the route with external inputs, such as notices to airmen (NOTAM), traffic data, and novel rules and data tables, from which the system identifies various kinds of hot-spots. The hot-spots include those that are aerodrome design based, those that are traffic related, and those that are temporal, based on short term closures or operational scenarios.

Abstract: An electric device includes: a first power domain; a second power domain; a third power domain, where during power-up, the third, the second, and the first power domains are configured to be powered up sequentially, where during standby-exit, the first, the second, and the third power domains are configured to be powered up sequentially; isolation paths that provide controlled signal transmission among the first, the second, and the third power domains, where each isolation path includes an isolation circuit between an input power domain and an output power domain of the isolation path; and a control circuit in the first power domain, where for each isolation path, the control circuit is configured to generate an isolation control signal for the isolation circuit, where the isolation circuit is configured enable or disable signal transmission along the isolation path.

Abstract: Techniques are provided for detecting an intrusion event in a network. At a gateway device in the network, performance parameters of the gateway device are monitored. Steady-state operations are defined based on expected performance of the device parameters. The steady-state operations are compared to the monitored device performance and other context parameters. A hybrid network intrusion detection technique is activated to determine a presence of the intrusion event for known and unknown attacks.

Abstract: Described herein are integrated circuit chips having test circuitry designed such that independently selectable testing of different power domains using a same scan chain compressor-decompressor circuit may be performed. Also disclosed herein are integrated circuit chips having test circuitry designed such that independently selectable testing of different power domains using multiple different scan chain compressor-decompressor circuits may be performed.

Abstract: Disclosed herein is a method of operating a system in a test mode. When the test mode is an ATPG test mode, the method includes beginning stuck-at testing by setting a scan control signal to a logic one, setting a transition mode signal to a logic 0, and initializing FIFO buffer for ATPG test mode. The FIFO buffer is initialized for ATPG test mode by setting a scan reset signal to a logic 0 to place a write data register and a read data register associated with the FIFO buffer into a reset state, enabling latches of the FIFO buffer using an external enable signal, removing the external enable signal to cause the latches to latch, and setting the scan reset signal to a logic 1 to release the write data register and the read data register from the reset state, while not clocking the write data register.

Abstract: Disclosed herein is logic circuitry and techniques for operation that hardware to enable the construction of first-in-first-out (FIFO) buffers from latches while permitting stuck-at-1 fault testing for the enable pin of those latches, as well as testing the data path at individual points through the FIFO buffer.

Abstract: Disclosed are methods, systems, and non-transitory computer-readable medium for a contextual transformation of an analytical model for an industrial internet of things (IIoT) edge node. For instance, the method may include receiving the analytical model from a cloud service; obtaining local data of the IIoT edge node; analyzing the local data to determine a situational context of the IIoT edge node; determining whether to transform the analytical model based on a fit between the analytical model and the situational context; and in response to determining to transform the analytical model, transforming the analytical model based on the situational context to derive a transformed analytical model.

Abstract: Disclosed herein is logic circuitry and techniques for operation that hardware to enable the construction of first-in-first-out (FIFO) buffers from latches while permitting stuck-at-1 fault testing for the enable pin of those latches, as well as testing the data path at individual points through the FIFO buffer.

Abstract: A method to bypass a voltage regulator of a system on a chip (SOC) comprising powering a first power domain using a voltage regulator; powering a second power domain using the voltage regulator; coupling a third power domain with an external voltage source; raising an external voltage supply from the external voltage source above a threshold level of the voltage regulator; coupling the first second power domains to the external voltage source; turning OFF the voltage regulator of the SOC after coupling the first power domain of the SOC and the second power domain of the SOC to the external voltage source; and powering the first power domain of the SOC, the second power domain of the SOC, and the third power domain of the SOC with the external voltage source, the external voltage source bypassing the voltage regulator.

Abstract: Computer-implemented methods for configuring an Industrial Internet of Things (IIoT) edge node in an IIoT network to perform one or more functions, comprising: performing a situation analysis to determine a required change in one or more of an analytical model, a runtime component, and a functional block of the IIoT edge node based on a change in the one or more functions; and automatically provisioning a new or updated functional module to the IIoT edge node, based on the situation analysis, the new or updated functional module including one or more components, wherein each component includes at least one of a rules set, a complex domain expression with respect to a process industry, an analytical model, and a protocol decoder.

Abstract: An electric device includes: a first power domain; a second power domain; a third power domain, where during power-up, the third, the second, and the first power domains are configured to be powered up sequentially, where during standby-exit, the first, the second, and the third power domains are configured to be powered up sequentially; isolation paths that provide controlled signal transmission among the first, the second, and the third power domains, where each isolation path includes an isolation circuit between an input power domain and an output power domain of the isolation path; and a control circuit in the first power domain, where for each isolation path, the control circuit is configured to generate an isolation control signal for the isolation circuit, where the isolation circuit is configured enable or disable signal transmission along the isolation path.

Abstract: A method to bypass a voltage regulator of a system on a chip (SOC) comprising powering a first power domain using a voltage regulator; powering a second power domain using the voltage regulator; coupling a third power domain with an external voltage source; raising an external voltage supply from the external voltage source above a threshold level of the voltage regulator; coupling the first second power domains to the external voltage source; turning OFF the voltage regulator of the SOC after coupling the first power domain of the SOC and the second power domain of the SOC to the external voltage source; and powering the first power domain of the SOC, the second power domain of the SOC, and the third power domain of the SOC with the external voltage source, the external voltage source bypassing the voltage regulator.

Abstract: In an embodiment, a method for managing self-tests in an integrated circuit (IC) includes: receiving built-in-self-test (BIST) configuration data; configuring a first clock to a first frequency based on the BIST configuration data; performing a first BIST test at the first frequency; configuring a second clock to a second frequency that is different from the first frequency; and performing a second BIST test at the second frequency.

Abstract: A circuit includes: a first power domain including: an isolation cell, a first selection circuit having inputs for receiving a first functional signal and a first test signal and an output for controlling the isolation cell, and a second selection circuit having inputs for receiving a second functional signal and a second test signal and an output coupled to a signal input of the isolation cell; a second power domain including: a first circuit having an input coupled to a signal output of the isolation cell, a first observation element coupled to the signal output of the isolation cell, and a second observation element coupled to an output of the first circuit; where, when in test mode, the first selection circuit controls the isolation cell based on the first test signal, and the second selection circuit provides the second test signal to the signal input of the isolation cell.

Abstract: Circuits and methods for testing voltage monitor circuits are provided. In one embodiment, a method includes setting voltage monitor circuits to test mode; setting, a monitor reference in each voltage monitor circuit, to a respective targeted threshold voltage using a corresponding trim code; ramping, a voltage provided to a subset of voltage monitor circuits, from a first voltage to a second voltage using a test voltage supply, voltages between the first voltage and the second voltage corresponding with targeted threshold voltages of the subset of voltage monitor circuits; determining, for each voltage monitor circuit in the subset of voltage monitor circuits, a voltage value of the test voltage supply resulting in a change in a logic state at an output of a corresponding voltage monitor circuit.