Abstract: Disclosed herein is circuitry for bypassing a medium voltage regulator during testing. The circuitry includes a low voltage regulator to, in operation, generate a first voltage within a first voltage range for powering first circuitry, and a medium voltage regulator to, in operation, generate a second voltage within a second voltage range greater than the first voltage range for powering second circuitry. A low voltage regulator bypass circuit generates a low voltage regulator bypass signal that operates to selectively bypass the low voltage regulator. A medium voltage regulator bypass circuit bypasses the medium voltage regulator as a function of the low voltage regulator bypass signal and an external voltage regulator select signal, the bypass of the medium voltage regulator being such that an external voltage can be applied to the second circuitry.

Abstract: A scan chain collects scan chain data from testing of a functional circuit and outputs a scan chain signal containing the scan chain data. A voltage monitor circuit operates to compare a supply voltage against a threshold and assert a reset signal when the supply voltage crosses the threshold. The reset signal resets a flip flop circuit whose output signal controls operation of a logic circuit that blocks passage of the scan chain signal to an integrated circuit probe pad and instead applies a constant logic signal to the probe pad indicating a voltage monitoring error.

Abstract: A circuit is for coupling test access port (TAP) signals to a Joint Test Action Group (JTAG) interface in an integrated circuit package. An nTRST pin receives a test reset signal, a TMS pin receives a test mode select signal, a testing test access port (TAP) has a test reset signal input and a test mode select signal input, and a debugging test access port (TAP) has a test reset signal input coupled to the nTRST pin and a test mode select signal input coupled to the TMS pin. An inverter has an input coupled to the nTRST pin and an output coupled to the test reset signal input of the testing TAP, and an AND gate has a first input coupled to the output of the inverter, a second input coupled to the TMS pin, and an output coupled to the test mode select input of the testing TAP.

Abstract: A JTAG interface in an IC includes a test mode select (TMS) pin receiving a TMS signal, a testing test access port (TAP) having a TMS signal input, a debugging test access port (TAP) having a TMS signal and glue logic coupled to receive a first output from the testing TAP and a second output from the debugging TAP. A flip-flop receives input from the testing TAP and the debugging TAP through the glue logic. A first AND gate has output coupled to the TMS signal input of the debugging TAP, and receives input from an output of the flip-flop and the TMS signal. An inverter has an input coupled to receive input from the flip-flop. A second AND gate has output coupled to the TMS signal input of the testing TAP, and receives input from the TMS signal and output of the inverter.

Abstract: Methods and systems are provided determining airport operations based on radio communications, the method includes: configuring a receiver of an aircraft to scan communication channels of different radio frequencies related to transmissions between air traffic control (ATC) and a set of aircrafts to determine one or more communication channels associated with the set of aircrafts in a coverage area to enable the receiver to monitor and receive air traffic control (ATC) communications of the set of aircraft; and processing, by a conversation extractor unit, the ATC communications to extract clearance information in the ATC communications, and to associate the clearance information with an identifier with each aircraft to create a table of timings of the clearance information to a particular aircraft with the identifier providing a view of airport operations.

Abstract: A test circuit is operable in ATPG mode and LBIST mode. The test circuit includes a clock selection circuit. The clock selection circuit includes clock logic circuitry to receive an LBIST mode signal and an ATPG mode signal and to generate an indication of whether the test circuit is operating in either the ATPG mode or the LBIST mode, a multiplexing circuit to receive an ATPG clock and a functional clock as input and output a selected one of the ATPG clock and the functional clock, and a clock gate circuit enabled in response to enable signals. The enable signals are an inverse of a selected one of the ATPG clock and the functional clock. The clock gate circuit receives the indication of whether the test circuit is operating in either the ATPG mode or the LBIST mode and generates a test clock as a function of the indication.

Abstract: A JTAG interface in an IC includes a test mode select (TMS) pin receiving a TMS signal, a testing test access port (TAP) having a TMS signal input, a debugging test access port (TAP) having a TMS signal and glue logic coupled to receive a first output from the testing TAP and a second output from the debugging TAP. A flip-flop receives input from the testing TAP and the debugging TAP through the glue logic. A first AND gate has output coupled to the TMS signal input of the debugging TAP, and receives input from an output of the flip-flop and the TMS signal. An inverter has an input coupled to receive input from the flip-flop. A second AND gate has output coupled to the TMS signal input of the testing TAP, and receives input from the TMS signal and output of the inverter.

Abstract: Systems and methods are provided for detecting a potential ambiguity in a sequence of clearance communications using conversational contextual information to identify potentially related communications. One exemplary method involves obtaining a first clearance communication associated with a first aircraft, obtaining a second clearance communication associated with a second aircraft, identifying a first conversational context associated with the first clearance communication, identifying a second conversational context associated with the second clearance communication, identifying a discrepancy between the first clearance communication and the second clearance communication based at least in part on the first conversational context and the second conversational context, and in response to identifying the discrepancy, generating a user notification at one of the first aircraft and the second aircraft.

Abstract: Methods and apparatus are provided for monitoring execution of air traffic control (ATC) conditional clearances for a user aircraft. The method monitors ATC clearances transmitted to all other aircraft across each communication channel from an airport. Every other aircraft is identified and the relevant data each ATC clearance is transcribed. A dependency table is generated for the user aircraft with the relevant data from every other aircraft. The dependency table identifies each relevant clearance that must be completed by all other aircraft before the user aircraft executes a conditional ATC clearance. The status of all relevant dependent ATC clearances is monitored and the user aircraft is informed of its conditional ATC clearance upon completion of the relevant dependent ATC clearances.

Abstract: A system and method for contextual tagging of data on at least one display associated with a vehicle is provided. The method includes: receiving data regarding the vehicle from at least one of a source of verbal data and a source of non-verbal data; determining a context associated with the data and a variable parameter associated with the context; determining a display element associated with the at least one display that corresponds to the determined variable parameter; generating a symbol for the display to display adjacent to the determined display element based on at least one of the determined context and the determined variable parameter; generating a selectable icon for the display to render adjacent to the symbol based on received verbal data; associating the received verbal data to the selectable icon; and outputting the received verbal data to an audio device based on a selection of the selectable icon.

Abstract: Computer-implemented methods for configuring an Industrial Internet of Things (IIoT) edge node in an IIoT network to perform one or more functions, comprising: performing a situation analysis to determine a required change in one or more of an analytical model, a runtime component, and a functional block of the IIoT edge node based on a change in the one or more functions; and automatically provisioning a new or updated functional module to the IIoT edge node, based on the situation analysis, the new or updated functional module including one or more components, wherein each component includes at least one of a rules set, a complex domain expression with respect to a process industry, an analytical model, and a protocol decoder.

Abstract: A method and system of monitoring aural and message alerts received during flight in an internet of things (IOT) cockpit of an aircraft generated by systems within the cockpit, the method includes: receiving a plurality of alerts which include at least one of an aural alert or message alert; applying a first natural language processing (NLP) process to the aural alert to convert the aural alert to a text alert consistent in structure with the message alert for aggregating together with the message alert to form a concatenated message alert; and identifying the context of the concatenated message alert by applying a second NLP process to the concatenated message alert in its entirety and subsequent tagging the concatenated message alert to associate a tagged message with a display element wherein the tagged message is a concatenated message.

Abstract: A scan chain collects scan chain data from testing of a functional circuit and outputs a scan chain signal containing the scan chain data. A voltage monitor circuit operates to compare a supply voltage against a threshold and assert a reset signal when the supply voltage crosses the threshold. The reset signal resets a flip flop circuit whose output signal controls operation of a logic circuit that blocks passage of the scan chain signal to an integrated circuit probe pad and instead applies a constant logic signal to the probe pad indicating a voltage monitoring error.

Abstract: Disclosed herein is circuitry for bypassing a medium voltage regulator during testing. The circuitry includes a low voltage regulator to, in operation, generate a first voltage within a first voltage range for powering first circuitry, and a medium voltage regulator to, in operation, generate a second voltage within a second voltage range greater than the first voltage range for powering second circuitry. A low voltage regulator bypass circuit generates a low voltage regulator bypass signal that operates to selectively bypass the low voltage regulator. A medium voltage regulator bypass circuit bypasses the medium voltage regulator as a function of the low voltage regulator bypass signal and an external voltage regulator select signal, the bypass of the medium voltage regulator being such that an external voltage can be applied to the second circuitry.

Abstract: A method of operating an electronic device during test mode operation of a duplicated voltage monitor includes sensing a functional supply voltage with a voltage monitor, deasserting an output of the voltage monitor if the functional supply voltage is exceeds a threshold, and asserting output of the voltage monitor if the functional supply voltage falls below the threshold. A test supply voltage is sensed with the duplicate voltage monitor, output of the duplicate voltage monitor is deasserted if the test supply voltage exceeds a threshold, and output of the duplicate voltage monitor is asserted if the test supply voltage falls below the threshold. Output of the duplicate voltage monitor is monitored to thereby determine the threshold based upon assertion of the output of the duplicate voltage monitor, and performing a logical operation between outputs of the voltage monitor and the duplicate voltage monitor to generate a power on reset signal.

Abstract: A test circuit receives LBIST and ATPG mode signals, and generates a first output as high when in ATPG or LBIST, and a second output as low when in ATPG or LBIST. A multiplexing circuit receives an ATPG clock and functional clock, and outputs one. A clock gate circuit includes a first latch receiving the second output, and an enable input receiving an inverse of the ATPG clock or functional clock. A second latch receives the first output, and has an enable input receiving the inverse of the ATPG clock or functional clock. The clock gate circuit includes a first AND gate receiving output of the first latch and ATPG clock or functional clock, a second AND gate receiving output of the second latch and the ATPG clock or LBIST clock, and an OR gate receiving outputs of the first and second AND gates, and generating a test clock.

Abstract: A test circuit is operable in ATPG mode and LBIST mode. The test circuit includes a clock selection circuit. The clock selection circuit includes clock logic circuitry to receive an LBIST mode signal and an ATPG mode signal and to generate an indication of whether the test circuit is operating in either the ATPG mode or the LBIST mode, a multiplexing circuit to receive an ATPG clock and a functional clock as input and output a selected one of the ATPG clock and the functional clock, and a clock gate circuit enabled in response to enable signals. The enable signals are an inverse of a selected one of the ATPG clock and the functional clock. The clock gate circuit receives the indication of whether the test circuit is operating in either the ATPG mode or the LBIST mode and generates a test clock as a function of the indication.

Abstract: A circuit is for coupling test access port (TAP) signals to a Joint Test Action Group (JTAG) interface in an integrated circuit package. An nTRST pin receives a test reset signal, a TMS pin receives a test mode select signal, a testing test access port (TAP) has a test reset signal input and a test mode select signal input, and a debuging test access port (TAP) has a test reset signal input coupled to the nTRST pin and a test mode select signal input coupled to the TMS pin. An inverter has an input coupled to the nTRST pin and an output coupled to the test reset signal input of the testing TAP, and an AND gate has a first input coupled to the output of the inverter, a second input coupled to the TMS pin, and an output coupled to the test mode select input of the testing TAP.

Abstract: A JTAG interface in an IC includes a test mode select (TMS) pin receiving a TMS signal, a testing test access port (TAP) having a TMS signal input, a debugging test access port (TAP) having a TMS signal and glue logic coupled to receive a first output from the testing TAP and a second output from the debugging TAP. A flip-flop receives input from the testing TAP and the debugging TAP through the glue logic. A first AND gate has output coupled to the TMS signal input of the debugging TAP, and receives input from an output of the flip-flop and the TMS signal. An inverter has an input coupled to receive input from the flip-flop. A second AND gate has output coupled to the TMS signal input of the testing TAP, and receives input from the TMS signal and output of the inverter.

Abstract: A logic built-in self-test (LBIST) circuit implements a pipeline scan enable launch on shift (LOS) feature. A first scan chain flip-flop has a scan enable input configured to receive a first scan enable signal. A logic circuit has a first input coupled to a data output of the first scan chain flip-flop and a second input coupled to receive the first scan enable signal. A second scan chain flip-flop has a scan input coupled to a scan output of the first scan chain flip-flop. A scan enable input of the second scan chain flip-flop is coupled to receive a second scan enable signal generated at an output of the logic circuit. The first and second scan chain flip-flops are clocked by a same clock signal.